LSI MPI SPECIFICATION Search Results

SYMFC929

Abstract: PC99 Fibre channel controller -40
Contextual Info: Symbios Dual Channel Fibre Solutions Introducing the Symbios Dual Channel 2 Gbaud SYMFC929 Controller and SYM44929LO/LH Host Adapter Board SYMFC929 Hardware Features • Highly-integrated 2 Gbaud dual-channel, SYMFC929 Single-Chip, Dual-Channel Fibre Channel Controller

MSP2000

Abstract: MIPS32 MSP3000 MSP4000 MSP5000 MSP5000-300-CB-A MSP-300 MIPS324KM
Contextual Info: Product Brief MSP5000 Multi-Service Processor Specifications Electrical LAN Interface Voice Engine Firmware • 369 pin PBGA • 2 Independent 10/100 Ethernet MACs MII or 7-wire • G.711, G.726, G.729a/b, G.723.1 • 16 KB instruction cache, 16 KB data cache

MSP5000

Abstract: MSP4000 voip ethernet single chip MSP2000 MIPS32 MSP3000 MSP4000-CB-A
Contextual Info: Product Brief MSP4000 Multi-Service Processor Specifications Electrical Security Engine • G.168 echo cancellers • 350 pin PBGA • Hardware accelerator for DES, 3DES, MD5, and SHA-1 • G.711-Fax, fax/modem tone detection • 32 Bit true random number generator

SAS2116

Abstract: SAS2004 Fusion-MPT Message Passing Interface MPI specification LSi SAS2108 LSISAS2008 SAS2108 LSISAS2004 SAS2Flash LSI Message Passing Interface MPI specification LSi SAS2008
Contextual Info: SAS2Flash Utility Quick Reference Guide Preliminary, Version 1.0 November 2009 Revision History Version and Date Version 1.0, November 2009 Description of Changes Initial release of the preliminary document. LSI, the LSI logo, and the Fusion-MPT are trademarks or registered trademarks of LSI Corporation or its subsidiaries. All other brand and product names may be trademarks of their respective companies.

Contextual Info: SHARP LZ95D71M L Z 9 5 D 7 1M Timing Pulse Generator LSI for CCD DESCRIPTION PIN CONNECTIONS The LZ95D71M is a CMOS timing generator LSI which provides timing pulses used to drive a CCD area sensor, in combination with the SSG LSI LZ95D52/M . FEATURES • Switchable between 410 000 pixels CCD and

LSI MPI Specification

Abstract: 000653 AMD64 SLP-300
Contextual Info: WarpDrive PCIe Solid State Storage Card Management Utility User Guide Revision 1.1 November 2010 Revision History Version and Date Description of Changes Revision 1.1, November 2010 Updated changes in the utility. Revision 0.1, March 2010 Initial advance release of this document.

md5 relay

Abstract: mips 4km MSP3000 MSP2000 LAN switch with HDLC BRECIS Communications routers data sheet MIPS32 MSP3000-CB-A MSP4000
Contextual Info: Product Brief MSP3000 Multi-Service Processor Specifications Electrical Security Engine Packet Engine Firmware Support • 350 pin PBGA • Hardware accelerator for DES, 3DES, MD5, and SHA-1 • AAL0, AAL1, AAL5 ATM SAR • Vcc 3.3V I/O, 1.8V core • 266 Mbps 3DES throughput

MSI MS-3

Contextual Info: SHARP LZ95D71M LZ95D 71M Timing Pulse Generator LSI for CCD DESCRIPTION PIN CONNECTIONS The LZ95D71M is a CMOS timing generator LSI which provides timing pulses used to drive a CCD area sensor, in combination with the SSG LSI LZ95D52/M . TOP VIEW 48-PIN Q FP

Contextual Info: / SPEC No. I ISSUE: EL068106 Allg. 31. 1994 SPECIFICATIONS ProductType lode1 100 No. Output LCD Common Driver LH1513AF $This tentative specifications contains 17 pages including the cover and appendix. If you have any objectionsplease contact us before issuing purchasing order.

GCC mep

Abstract: MeP toshiba Toshiba MeP mep toshiba programming mep toshiba architecture Toshiba MPI tool mep toshiba Instruction mep toshiba programming manual C compiler manual toshiba MeP MEP-12T user manual
Contextual Info: MPI User Extension Manual MPI User Extension Manual Toshiba Corporation, Semiconductor Company doc-Ver. 1.30 Semiconductor Company TOSHIBA MEPUM03012-E30 i MPI User Extension Manual RESTRICTIONS ON PRODUCT USE • Toshiba Corporation, and its subsidiaries and affiliates collectively "TOSHIBA" , reserve the right to make changes to

LSISAS2008

Abstract: LSISAS2004 LSISAS2108 Fusion-MPT Message Passing Interface MPI specification Fusion-MPT Message Passing Interface Specification LSISAS SAS2008 DG072A9BB7 LSI sas2008 lsisas2008 datasheet
Contextual Info: SAS2 Integrated RAID Solution User Guide Version 1.0 July 2009 Revision History Version and Date Version 1.0, July 2009 Description of Changes Initial release of this document. LSI, the LSI logo, Fusion-MPT, Integrated RAID, Integrated Mirroring, and Integrated Striping are trademarks or registered trademarks of LSI Corporation or its subsidiaries. SPARC is a registered trademark of SPARC International, Inc. Linux is a registered trademark of Linus Torvalds. Windows and MS-DOS are registered trademarks of Microsoft Corporation. All other brand and product names may

Contextual Info: Interconnection Systems Selection Guide 82750 Revised 7-95 Product Facts High-Speed Standard Edge Connectors • 1:1 signal-to-ground ratio ■ Designed for signal transmissions with rise and fa ll times of 0.5 nanoseconds or greater 'A'V3' ■ 40 signal/ground pairs per

UM91252

Contextual Info: U M O U M 9 1 2 S S /2 S 6 Memory Tone/Pulse Dialer Features • Transmute and Receivemuter on chip ■ The ten 18-digit repertory memory and 24-digit redialing memory can be used in either tone or pulse mode ■ The repertory memory can be stored in ON-Hook

Am79C30A

Abstract: "Am79C30" am79c30a preliminary
Contextual Info: a Preliminary Am79C30A/32A Advanced Micro Devices Digital Subscriber Controller DSC ISDN Data Controller (IDC) DISTINCTIVE CHARACTERISTICS • Combines CCITT 1.430 S/T Interface trans­ ceiver, D-channel LAPD processor, and audio processor (DSC only) in a single chip

Contextual Info: NOV 2 1 199» n Preliminary Am79C30A Advanced Micro Devices Digital Subscriber Controller DSC DISTINCTIVE CHARACTERISTICS • Combines CCITT 1.430 S/T Interface Trans­ ceiver, D-channel LAPD Processor, Audio Processor (DSC only), and IOM-2 Interface

HD637B01Y0

Abstract: HD6301YO HD637A01YOC HD63701 HD63701Y0 marking code P5A P73 HD637A01Y0 p5a TRANSISTOR MARKING aval 27256 LM 784 OP
Contextual Info: HD63701Y0, HD637A01Y0,-HD637B01 YO Limiting Supplies. For Development Only. Description The HD63701Y0 is a CMOS 8-bit single-chip micro­ computer unit with 16k-byte EPROM, programmed by the same method as the standard 27256 EPROM. It is available in a ceramic package. The userprogrammable on-chip EPROM reduces lead time

SC4105

Abstract: preamplifier 4558 circuit diagram DIN 3967 617-2240 IC1 4558 h3 0925 SC430 ic 4558 audio diagram LM 4138 BTA 2087-0
Contextual Info: NOV 2 1 199» Preliminary ÎI Am79C30A Advanced Micro Devices Digital Subscriber Controller DSC DISTINCTIVE CHARACTERISTICS • Combines CCITT 1.430 S/T Interface Trans­ ceiver, D-channel LAPD Processor, Audio Processor (DSC only), and IOM-2 Interface

transistor marking p5t

Contextual Info: HD63701Y0, HD637A01Y0,-HD637B01Y0 Limiting Supplies. For Development Only. Description The HD63701Y0 is a CMOS 8-bit single-chip micro­ computer unit with 16k-byte EPROM, programmed by the same method as the standard 27256 EPROM. It is available in a ceramic package. The userprogrammable on-chip EPROM reduces lead time

4560 JRC

Abstract: jrc 4560 4560 d JRC MJ-064 nju6468
Contextual Info: NJU6468 P R E L IMI N A R Y 8 - C H A R A C T E R 2 - L I N E D O T M A T R I X L C D C O N T R O L L E R D R I V E R W I T H E X T E N S I O N • GENERAL DESCRIPTION The NJU6468 is a Dot Matrix LCD controller driver for 8-character 2-line display with extension function up to

FD1793

Abstract: FD50A TEAC FLOPPY CIRCUIT DIAGRAM schematic teac floppy spindle motor FD650 stepping motor teac shugart 801 SA850 western digital FD1793 RFD4000
Contextual Info: Advanced M icro Oevices, Inc. Am95/6120 Dual-Density Floppy Disk Controller User’s Manual 059901341-001 $ 15.00 REVISION RECORD REVISION 01 DESCRIPTION Preliminary Issue 7/1/803 A Manuai Release (8 /1 5 /8 0 B Manual Updated To Incorporate Additional Jumper Information

DB14-000174

Abstract: Fusion-MPT Message Passing Interface MPI specification DB14-000174-00 LSIFC919 AA13 PAR64 PC01 fixed burst PBSRAM Fusion-MPT Message Passing Interface Specification LSI Message Passing Interface MPI specification
Contextual Info: TECHNICAL MANUAL LSIFC919 Single Channel Fibre Channel I/O Processor Revision 2.1 October 2002 DB14-000151-02 Electromagnetic Compatibility Notices This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:

DB14-000174-00

Abstract: DB14-000174 Fusion-MPT Message Passing Interface MPI specification LSIFC919 LSIFC929 PAR64 PC01 ACK64 Fusion-MPT Message Passing Interface Specification
Contextual Info: Technical Manual LSIFC919 Single Channel Fibre Channel I/O Processor Revision 2.0 October 2001 DB15-000151-01 Electromagnetic Compatibility Notices This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:

Fusion-MPT Message Passing Interface MPI specification

Abstract: Fusion-MPT Message Passing Interface Specification LSI Message Passing Interface MPI specification DB14-000174 DB14-000174-00 LSIFC929 PAR64 PC01 LSI "message passing interface specification" Fusion-MPT Message Passing Interface Specification doorbell
Contextual Info: Technical Manual LSIFC929 Dual Channel Fibre Channel I/O Processor Revision 2.0 August 2001 S14073 Electromagnetic Compatibility Notices This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: 1. 2. This device may not cause harmful interference, and

74LS189 equivalent

Abstract: 74LS200 AmZ8036 Z8104 74LS300 AM9511 Am2505 27s13 54S244 27LS00
Contextual Info: Advanced Micro Devices Condensed Catalog 1981 Advanced Micro Devices, Inc. Advanced Micro Devices reserves the right to make changes in its products without notice in order to improve design or performance characteristics. The company assumes no responsibility for the use of any circuits described herein.