LS561A Search Results

Contextual Info: SN54ALS560A, LS561A, SN74ALS560A, LS561A SYNCHRONOUS 4 BIT COUNTERS WITH 3-STATE OUTPUTS D 2 6 6 1 , DECEMBER 1982 C arry O u tp u t fo r n-B it C ascading B uffe r-T ype O u tp u ts D rive Bus Lines D irectly REVISED M A Y 1 9 8 6 SN 54A LS560A, S N 54A LS561A . . . J PACKAGE

Q1038

Abstract: SN74ALS561A SN54ALS561A sn54als516
Contextual Info: LS561A, LS561A SYNCHRONOUS 4-BIT COUNTERS WITH 3-STATE OUTPUTS D 2 6 6 1 , D E C E M B E R 19 82 - R E V IS E D M A Y 1986 Carry O utput for n-Bit Cascading Buffer-Type Outputs Drive Bus Lines Directly S N S 4A LS561A . . . J PACKAGE SN 74A LS 561A . . . D W O R N PACKAGE

SN74ALS560

Abstract: SN74ALS560A SN54ALS561A SN74ALS561A
Contextual Info: SN54ALS560A, SN54ALS561 A, SN74ALS560A, SN74A LS561A SYNCHRONOUS 4 BIT COUNTERS W ITH 3-STATE OUTPUTS D 2 6 6 1 , DECEMBER 1 9 8 2 C a rry O u tp u t fo r n -B it C a s c a d in g R E V IS E D M A Y 1 9 8 6 S N 5 4 A L S 5 6 0 A , S N 5 4 A L S 5 6 1 A . . . J P AC KA G E

561A

Abstract: SN54ALS560 sn74als560
Contextual Info: TYPES SN54A LS560A , SN54A LS561A , SN74A LS560A , SN74A LS561A SYNCHRONOUS 4-BIT COUNTERS W ITH 3 STATE OUTPUTS D 2 6 6 1 , DECEMBER 1 9 8 2 -R E V IS E D DECEMBER 1 9 8 3 • S N 54A LS 560A , S N 54A LS 561A Carry Output for n-BIt Cascading J PACKAGE S N 7 4 A L S 5 6 0 A , S N 7 4 A L S 5 6 1 A . . . N PACKAGE

M74ALS374P

Abstract: dd127 4d40t
Contextual Info: MITSUBISHI iDGTL LOGIC} TI 1mF | bSLHÖ27 D0155E5 5 MITSUBISHI ALSTTLs ,oC* M 74A LS374P OCTAL D-TYPE EDGE-TRIGGERED FLIP FLOP W ITH 3-STATE OUTPUT NONINVERTED 6249827 MITSUBISHI 9 1D 12525 (DGTL LOGIC) DESCRIPTION D PIN CONFIGURATION (TOP VIEW) T h e M 7 4 A L S 3 7 4 P is a s e m ic o n d u c to r in te g ra te d c irc u it

D0-15L

Abstract: LS74AD
Contextual Info: 7 z1 % > -'0 '7 -¿ ? S ' M 74ALS873AP ¡C' 3< DUAL 4 -B IT D-TYPE TRANSPARENT LATCH W ITH 3-STATE OUTPUT NONINVERTED 50t° CDGTL LOGIC) DESCRIPTION PIN CONFIGURATION (TOP VIEW) DIR EC T RESET , p " IN P U T I M ° O UTPUT } -q C O N TR O L IN PU T E c

M74ALS193P

Abstract: TF2N 154027
Contextual Info: MITSUBISHI I -CDGTL L O G I C ? =11 De | bEMTñE? □□12454 ñ T~ ^ MITSUBISHI ALSTTLs . M74ALS193P SYNCHRONOUS PRESETTABLE U P /D O W N 4 -B IT B IN A R Y COUNTER 6248827 MITSUBISHI ÍDGTL LOGIC DESCRIPTION The M74ALS193P is a semiconductor integrated circuit

dd127

Contextual Info: D e | hS4clflE!7 GG1E3M7 7 |~~ MIT SUB ISHI íDGTL LOGIC} TI MITSUBISHI ALSTTLs M74ALS15AP 6249827 MITSUBISHI <DGTL LOGI C 91D 12347 D TRIPLE 3-IN P U T POSITIVE AND GATE W ITH OPEN COLLECTOR OUTPUT DESCRIPTION Th e M 7 4A L S 15A P is a se m ic o n d u c to r in teg rated circu it

1e4d

Abstract: ls151p LS29 LS245 74als15
Contextual Info: MITSUBISHI -CDGTL LOGIC} TI -DE | 00123^0 S MITSUBISHI ALSTTLs ,o c* M 7 A L S ! 4 5 1 JP T-66-21-53 8-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER WITH STROBE 6249827 MITSUBISHI DGTL LOGIC r DESCRIPTION T h e M 7 4A L S 151 P is a sem iconductor in teg rated circuit

LS353P

Abstract: d12518 74ALS04A
Contextual Info: MI TSU BISHI {DGTL LOGIC! TI » F l b5MTÖ27 0Q1SS1Ö fl | ~ MITSUBISHI ALSTTLs M 74A LS353P o O ° DUAL 4 -U N E TO 1-LINE DATA SELECTOR/MULTIPLEXER WITH 3-STATE OUTPUT INVERTED 6249827 MITSUBISHI 9 1 D 12518 (DGTL LOGI C) DESCRIPTION T h e M 7 4A L S 353 P is a sem iconductor integrated circuit

Contextual Info: LS561A, LS561A SYNCHRONOUS 4-BIT COUNTERS WITH 3-STATE OUTPUTS SD A S2 2 5 A - DECEM BER 1982 - REVISED JANUARY 1995 Carry Output for n-BIt Cascading Buffer-Type Outputs Drive Bus Lines Directly Choice of Asynchronous or Synchronous Clearing and Loading

74als05

Abstract: 74als245a LS574A
Contextual Info: MITSUBISHI íDGTL I LOGIC} _ TI 6249827 MITSUBISHI D eT | bEMTflE? □D lE 7t.l t I MITSUBISHI ALSTTLs M 74ALS1 6 2 3 AP DGTL LOGIC - 91D 12761 D OCTAL BUS TRANSCEIVER W ITH 3-STATE OUTPUT (NONINVERTED) 7 = 5 2 ? -3 / DESCRIPTION PIN CONFIGURATION (TOP VIEW)

diode ED 74a

Abstract: se 115n 74ALS04A
Contextual Info: MM MITSUBISHI -CDGTL LOGIC} T1 6249827 M I T S U B I S H I {D G T L 9 1 D 1 23 6 3 D GG123b3 S |~ MITSUBISHI ALSTTLs LOGIC M 74A LS 33A P QUADRUPLE 2-IN P U T POSITIVE NOR BUFFER W ITH OPEN COLLECTOR OUTPUT DESCRIPTION The M 7 4A L S 33A P is a se m ic o n d u c to r in teg rated circu it

1d12407

Contextual Info: MITSUBISHI -CDGTL LOGICI TI TËj|t,EMTâ27 DDiaHO? □ MITSUBISHI ALSTTLs o c ^ , * 0 M 7 4 A LS 15 8 P 6249827 MITSUBISHI CDGTL L O GI C :' • T-66-21-51 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER INVERTED) 9 1 D 12407 DESCRIPTION The M 74ALS158P is a sem iconductor integrated circuit

74ALS04A

Abstract: LS08D 74ALS37A LS193D
Contextual Info: MITSUBISHI -CDGTL LOGIC} 1>Ë| bEM^ôE? QaiaasT 3 | ” =11 MITSUBISHI ALSTTLs M 74A LS 30A P 6249827 MITSUBISHI D G T L LOGIC 91D D 1235 9 SINGLE 8-IN P U T POSITIVE NAND GATE | 5 — DESCRIPTION PIN CONFIGURATION (TOP VIEW) The M74ALS30AP is a semiconductor integrated circuit

LS192P

Abstract: 74ALS38
Contextual Info: MITSUBISHI -CDGTL LOGIC]-*!! bSMTñí? D 0 1 5 4 5 G □ |"~ MITSUBISHI ALSTTLs iV jG Ï M 74A LS192P ,* o o SYNCHRONOUS PRESETTABLE UP/DOW N DECADE COUNTER 6249827 M1 t s H j e h s h i 9 1D D G fL ~ ~ L d G ~ i~ cJ ~ DESCRIPTION 12450 D PIN CONFIGURATION (TOP VIEW