LS232 Search Results

SN54AHCT04

Abstract: SN74AHCT04 94A7
Contextual Info: SN54AHCT04, SN74AHCT04 HEX INVERTERS SC LS232G - O C TO B E R 1995 - REVISED JU LY 1997 SN54AHCT04 . . . J OR W PACKAGE S N 7 4 A H C T 0 4 . . . D, DB, DGV, N, OR PW PACKAGE TOP VIEW • Inputs Are TTL-Voltage Compatible • EPIC (Enhanced-Performance Implanted

ax doc hen nit

Contextual Info: LS232A, LS232A 16 x 4 ASYNCHRONOUS FIRST-IN FIRST OUT MEMORIES D2876, OCTOBER 1985-REVISED APRIL 1986 SN 54A LS2 32A . . . J PACKAGE SN 74A LS232A D O R N PACKAG E Independent Asynchronous Inputs and Outputs C 1 U l6 fu llQ 2 15 ld c k C 3 14 DOC 4

at90s

Abstract: ATTINY25 timer AT90LS2323 AT90LS2343 AT90S2323 AT90S2343
Contextual Info: AVR503: Replacing AT90S/LS2323 or AT90S/LS2343 with ATtiny25 Features • • • • • • • • • General Porting Considerations Memories System Clock and Clock Options System Control and Reset Registers Interrupt Vectors I/O Ports Memory Programming

Contextual Info: LS232A, LS232A 16 X ASYNCHRONOUS FIRST-IN FIRST-OUT MEMORIES D 2 8 7 6 , OCTOBER 1 9 8 5 - • Independent A sy n c h ro n o u s Inputs and O u tp u ts • Package O ption s Include P lastic "S m a ll O u tlin e " Packages, C eram ic C hip Carriers,

Contextual Info: LS2323 DUAL LINE RECEIVER SDLS965 − OCTOBER 2004 D Single 5-V Supply D ±100-mV Sensitivity D For Application as: D D D D D D D PACKAGE TOP VIEW 1OUT COMSTRB 1LINE GND − Single-Ended Line Receiver − Gated Oscillator − Level Comparator Adjustable Reference Voltage

Contextual Info: Errata • • • • • Releasing Reset Condition without Clock Clearing Lock-bits at High VCC or Temperature Wrong Clearing of XTRF in MCUSR Reset during EEPROM Write Serial Programming at Voltages below 3.0 Volts 5. Releasing Reset Condition without Clock

atmel 1004A

Abstract: at90s AT90LS2323 AT90LS2343 AT90S2323 AT90S2343 CS02
Contextual Info: Features • • • • • • • • • • • • • • • • • • • • Utilizes the AVR Enhanced RISC Architecture AVR - High Performance and Low Power RISC Architecture 118 Powerful Instructions - Most Single Clock Cycle Execution 2K bytes of In-System Programmable ISP Flash

NHC3011-5

Abstract: POWER 12v 28V 3A 60W DC-DC DNA 1005 SPM5 MAP55-1024 MPB125 powcom "power-one" spm5 LM1501 MAP110-4004
Contextual Info: 2006 PRODUCT UPDATE AC-DC Power Supplies Courtesy of Steven Engineering, Inc.-230 Ryan Way, South San Francisco, CA 94080-6370-Main Office: 650 588-9200-Outside Local Area: (800) 258-9200-www.stevenengineering.com Infrastructure Power for an On-Demand World

AT90S2343-10

Abstract: AT90LS2323 AT90LS2343 AT90S2323 AT90S2343 AT90S2323-10PI
Contextual Info: Features • Utilizes the AVR RISC Architecture • AVR – High-performance and Low-power RISC Architecture • • • • • • • • – 118 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General-purpose Working Registers

AT90LS2323

Abstract: AT90LS2343 AT90S2323 AT90S2343
Contextual Info: Features • Utilizes the AVR RISC Architecture • AVR – High-performance and Low-power RISC Architecture • • • • • • • • – 118 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General-purpose Working Registers

4x4 keypad c code atmega16

Abstract: ATmega16 IR remote control 4x4 keypad c code atmega32 4x4 keyboard for atmega32 AVR atmega16 matrix keypad interface gps with AVR atmega128 AVR atmega16 led matrix atmega 8 c coding AVR atmega8515 led matrix atmega 8 c coding for motor control
Contextual Info: AVR Flash Microcontroller ATMEL CORPORATION AVR Flash Microcontroller: Product Line Reference September 2003 Edition Table of Contents 1 2 3 4 ATtiny Product Family . 2

atmel 806

Abstract: Atmel 8051 Microcontrollers cisc architecture in 8051 90S1200 90S2313 90S2343 AT90S8515 EQ-8051-ST1 SS-90S8515-P Micro-Pro 51
Contextual Info: Atmel AVR Microcontroller Family - Product Selection Guide DEVICE 90S1200 90S2313 90S2343 90S4414 90S8515 90S2333 90S8535 MEGA603 MEGA103 FLASH Bytes 1K 2K 2K 4K 8K 2K 8K 64K 128K EEPROM (Bytes) 64 128 128 256 512 128 512 2K 4K SRAM (Bytes) 128 128 256 512

Contextual Info: Errata • • • • Wrong Clearing of XTRF in MCUSR Reset During EEPROM Write Verifying EEPROM in System Serial programming at voltages below 3.0 Volts 4. Wrong Clearing of XTRF in MCUSR The XTRF flag in MCUSR will be cleared when clearing the PORF-flag. The flag

atmel 111

Abstract: STK200 tm 2313 hitachi 8P STK200 circuit atmel111 74HC573 20 PIN 8 pin ic used in laptop 8515 microcontroller lm317 a 8 terminal
Contextual Info: Table of Contents Section 1 Introduction . 1-1 1.1 Device Support .1-1 Section 2

Contextual Info: Features * Utilizes the AVR RISC Architecture * AVR - High-performance and Low-power RISC Architecture - 118 Powerful Instructions - Most Single Clock Cycle Execution - 32 x 8 General Purpose Working Registers - Up to 10 MIPS Throughput at 10 MHz * Data and Nonvolatile Program Memory

ST93C86

Abstract: d87c257 D27128 NEC AM27020 d2732 UPD6252 ST93C76 NEC D2732 microchip CY7C63000 GAL20AS
Contextual Info: GALEP 4 - device support for GALEP32 software version 1.14.12 ! Bauteile im DIL Gehäuse benötigen keinen Adapter ! Devices in DIL package do not require any adapter -EEPROM

STK200

Abstract: STK200 circuit atmel 111 atmel 2313 20pin 74FHC573 MEGA103 AT90S1200 AT90S2313 AT90S4414 AT90S8515
Contextual Info: STK200 Starter Kit User Guide - February 1999 R Table of Contents Section 1 Introduction . 1-1 1.1 Device Support .1-1

atmel 1138

Abstract: 1273A-04
Contextual Info: Introduction This document contains the latest information about the AVR data book and the AVR data sheets. All references to the data book refers to the August 1999 version of the “AVR RISC MICROCONTROLLER DATA BOOK”. All references to the AVR data sheets refer to the latest version of the AVR data

48 VOLT 20AMP battery charger

Abstract: lm1785 BP1601 ZY2105 qts48t46096 PSR53-7 HBD060ZGE-A MPB150 40IMX35D05D15-8 FXP7000-48-S
Contextual Info: Z-One Digital Power Analog POL Isolated DC-DC Front Ends Chassis Mount PoE Ruggedized CompactPCI Renewable Energy Network Power Systems Intelligent Controls 2010 Online Product Update Table of Contents Point-Of-Load Conversion & Management Bus Programmable Digital POL Solutions

AT90S2323-10PC

Abstract: 1004B SEV 1011 sii S AT90LS2323 AT90LS2343 AT90S2323 AT90S2343
Contextual Info: Features • Utilizes the AVR RISC Architecture • AVR - High-performance and Low-power RISC Architecture • • • • • • • • – 118 Powerful Instructions - Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Up to 10 MIPS Throughput at 10 MHz

Contextual Info: LS2323 DUAL LINE RECEIVER SDLS965 − OCTOBER 2004 D Single 5-V Supply D ±100-mV Sensitivity D For Application as: D D D D D D D PACKAGE TOP VIEW 1OUT COMSTRB 1LINE GND − Single-Ended Line Receiver − Gated Oscillator − Level Comparator Adjustable Reference Voltage

Contextual Info: S Series Data Sheet 100 Watt DC-DC and AC-DC Converters Features • RoHS lead-free-solder and lead-solder-exempted products are available. • Class I equipment • Extremly wide input voltage ranges from 8 to 385 VDC, and 85 to 264 VAC, 47 to 440 Hz • Input over- and undervoltage lockout

sn74ls23

Contextual Info: LS2323 DUAL LINE RECEIVER SDLS965 − OCTOBER 2004 D Single 5-V Supply D ±100-mV Sensitivity D For Application as: D D D D D D D PACKAGE TOP VIEW 1OUT COMSTRB 1LINE GND − Single-Ended Line Receiver − Gated Oscillator − Level Comparator Adjustable Reference Voltage

LWN2880-6

Contextual Info: Z-One Digital Power Analog POL Isolated DC-DC Front Ends Chassis Mount Modular Products 2010 ONLINE AC-DC & DC-DC POWER SOLUTIONS PRODUCT UPDATE PoE CompactPCI Ruggedized Table of Contents Point-Of-Load Conversion & Management Bus Programmable Digital POL Solutions