LPDDR2 PHY Search Results
LPDDR2 PHY Result Highlights (4)
| Part | ECAD Model | Manufacturer | Description | Download | Buy |
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| DP83TC811SWRNDTQ1 |
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Low-power automotive PHY 100BASE-T1 Ethernet physical layer transceiver 36-VQFNP -40 to 125 |
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| DP83TC811SWRNDRQ1 |
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Low-power automotive PHY 100BASE-T1 Ethernet physical layer transceiver 36-VQFNP -40 to 125 |
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| TSB14AA1AIPFB |
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IEEE 1394-1995, 3.3V, 1-port, 50/100Mbps, Backplane PHY 48-TQFP |
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| TIDA-00207 |
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EN55011 Compliant, Industrial Temperature, 10/100Mbps Ethernet PHY Brick Reference Design |
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LPDDR2 PHY Price and Stock
Lattice Semiconductor Corporation LPDDR2-PHY-AVE-UIP LPDDR2 SDRAMCTRLR AVANTE SNGL |
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LPDDR2-PHY-AVE-U | No Container | 1 |
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Lattice Semiconductor Corporation LPDDR2-PHY-AVE-UTIP LPDDR2 SDRAMCTRLR AVANTE SITE |
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LPDDR2-PHY-AVE-UT | No Container |
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LPDDR2-PHY-AVE-UT |
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Lattice Semiconductor Corporation LPDDR2-PHY-AVE-USIP LPDDR2 SDRAMCTRLR AVANT-E 1YR |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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LPDDR2-PHY-AVE-US | No Container |
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LPDDR2-PHY-AVE-US |
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LPDDR2 PHY Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
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Contextual Info: APPLICATION NOTE ARMADA 16X Memory Controller Configuration and Tuning 1. Overview The ARMADA 16x Memory Controller Unit MCU supports LPDDR1, DDR2, and LVDDR2. It does not support LPDDR2. It is critical that the MCU be programmed correctly to ensure system stability. |
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MV-S301544-00) MV-S301989-00 | |
MPS 0715
Abstract: mps 0705
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NB675 NB675 QFN21 MPS 0715 mps 0705 | |
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Contextual Info: Zynq-7000 SoC and 7 Series Devices Memory Interface Solutions v2.0 DS176 December 18, 2013 Advance Product Specification Introduction LogiCORE IP Facts Table The Xilinx 7 series FPGAs memory interface solutions cores provide high-performance connections to DDR3 |
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Zynq-7000 DS176 | |
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Contextual Info: che.com 7 Series FPGAs Memory Interface Solutions v2.0 DS176 June 19, 2013 Advance Product Specification Introduction LogiCORE IP Facts Table The Xilinx 7 series FPGAs memory interface solutions cores provide high-performance connections to DDR3 and DDR2 |
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DS176 | |
lpDDR2 SODIMMContextual Info: 7 Series FPGAs Memory Interface Solutions v1.9 DS176 March 20, 2013 Advance Product Specification Introduction LogiCORE IP Facts Table The Xilinx 7 series FPGAs memory interface solutions cores provide high-performance connections to DDR3 and DDR2 SDRAMs, |
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DS176 lpDDR2 SODIMM | |
Micron TechnologyContextual Info: Micron DRAM Products Overview August 2013 John Quigley – Micron FAE 2012 Micron Technology, Inc. All rights reserved. Products are warranted only to meet Micron’s production data sheet specifications. Information, products, and/or specifications are subject to change without notice. All information is provided on an “AS IS” basis without warranties of any kind. Dates are estimates only. Drawings are not to scale. Micron and |
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20Note/DRAM/TN4102 TN-41-04: TN-41-13: TN-46-02: TN-46-06: TN-46-11: TN-46-14: TN-47-19: TN-47-20: Micron Technology | |
sony IMX 161
Abstract: STMP3780 toshiba 16GB Nand flash emmc Cortex-A8 MIPI Toshiba emmc i.mx258 MC9S08GP32 sony cmos sensor imx 17 OV56 Sony IMX283
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AR6003
Abstract: SoC ARM cortex 64bit Hardware Manual
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ARM11 150MJuly AR6003 SoC ARM cortex 64bit Hardware Manual | |
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Contextual Info: Freescale Semiconductor Application Note Document Number: AN4397 Rev. 1, 06/2013 Common Hardware Design for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite The i.MX 6Quad, i.MX 6Dual, i.MX 6DualLite, and i.MX 6Solo families of applications processors represent Freescale Semiconductor’s ARM Cortex -A9 based |
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AN4397 | |
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Contextual Info: Pin Information for the Arria V 5AGXFB7 Device Version 1.2 Note 1 Bank Number VREF PinName/Function (2) VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 |
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Contextual Info: Pin Information for the Arria V 5AGXMB5 Device Version 1.4 Note 1 Bank Number VREF PinName/Function (2) VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 |
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Contextual Info: Pin Information for the Arria V 5AGXMA7 Device Version 1.2 Note 1 Bank Number VREF PinName/Function (2) VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 |
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Contextual Info: Pin Information for the Arria V 5AGXFB5 Device Version 1.2 Note 1 Bank Number VREF PinName/Function (2) VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 |
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Contextual Info: Pin Information for the Arria V 5AGXMA5 Device Version 1.2 Note 1 Bank Number VREF PinName/Function (2) VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 |
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Contextual Info: Pin Information for the Arria V 5AGXMB3 Device Version 1.6 Note 1 Bank Number VREF PinName/Function (2) VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 |
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F1517 | |
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Contextual Info: Pin Information for the Arria V 5AGXMB7 Device Version 1.4 Note 1 Bank Number VREF PinName/Function (2) VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 |
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Contextual Info: Pin Information for the Arria V 5AGTMC3 Device Version 1.0 Note 1 Bank Number VREF PinName/Function (2) VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 |
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Contextual Info: Pin Information for the Arria V 5AGXMB1 Device Version 1.6 Note 1 Bank Number VREF PinName/Function (2) VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 |
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F1517 | |
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Contextual Info: Pin Information for the Arria V 5AGXMA3 Device Version 1.0 Note 1 Bank Number VREF PinName/Function (2) VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 |
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Contextual Info: Pin Information for the Arria V 5AGXMA1 Device Version 1.0 Note 1 Bank Number VREF PinName/Function (2) VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 |
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Contextual Info: Pin Information for the Arria V 5ASXBB5 Device Version 1.0 Note 1 Bank Number VREF PinName/Function (2), (3) VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 |
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Contextual Info: Pin Information for the Arria V 5AGTMD3 Device Version 1.2 Note 1 Bank Number VREF PinName/Function (2) VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 |
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F1152 F1517 | |
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Contextual Info: Pin Information for the Arria V 5ASXBB3 Device Version 1.0 Note 1 Bank Number VREF PinName/Function (2), (3) VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 |
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CK3AContextual Info: Pin Information for the Arria V 5AGTFD3 Device Version 1.0 Note 1 Bank Number VREF PinName/Function (2) VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 |
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