LOW23 Search Results

Contextual Info: ANALOG DEVICES FEATURES PERFORMANCE 25 ns Instruction Cycle Tim e 40 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture A llow s Dual Operand Fetches in Every Instruction Cycle M ultifunction Instructions

2184S

Contextual Info: ANALOG DEVICES Preliminary Technical Data FEATURES PERFORMANCE 25 ns Instruction Cycle Tim e 40 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture A llow s Dual Operand Fetches in Every Instruction Cycle

transistor d1913

Abstract: all max 8734 circuit and black diagram D1915 Transistors circuit diagram of MOD 100 counter using ic 7490 MIOS12 MPC556-Compatible TRANSISTOR BC 313-10 motorola transistor 4810 h24 fop 630 motorola 1550
Contextual Info: MPC561/3RM/D MPC561/MPC562 / MPC563/MPC564 REFERENCE MANUAL Revised 29 June 2001  Copyright 2001 MOTOROLA; All Rights Reserved MPC561/3RM/D MPC561/MPC562 / MPC563/MPC564 REFERENCE MANUAL Revised 29 June 2001  Copyright 2001 MOTOROLA; All Rights Reserved

adsp 2186 instruction set

Abstract: ka 2186 quartz kds klb x5 LQFP-100 footprint 001C ADSP-2100 ADSP-2181 ADSP-2186 2186B
Contextual Info: ANALOG DEVICES FEATURES PERFORMANCE 25 ns Instruction Cycle Tim e 40 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture A llow s Dual Operand Fetches in Every Instruction Cycle M ultifunction Instructions

Contextual Info: ANALOG DEVICES Preliminary Technical Data FEATURES PERFORMANCE 25 ns Instruction Cycle Tim e 40 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture A llow s Dual Operand Fetches in Every Instruction Cycle

IMV2

Abstract: E1 AMI HDB3 decoder 13003 T3FL 5ulz
Contextual Info: VLSI Techno lo gy, in c . VP14Q574 T1/E1 QUAD LINE INTERFACE UNIT • Meets Bellcore TR499 and AT&T 62411 specifications FEATURES • Four analog PCM line interfaces for T 1 and E1 CEPT applications

74S189

Abstract: N3101AN N74S189D N3101
Contextual Info: Philips Components-Signetics Document No. 853-0152 8 2 S 2 5 / 3 1 0 1 A ECN No. 86487 / 7 4 S 1 8 9 64-bit TTL bipolar RAM Date of Issue November 11, 1986 Status Product Specification Memory Products PIN CONFIGURATION DESCRIPTION APPLICATIONS This family of Read/Write Random

BGA PACKAGE thermal resistance

Abstract: A112 G38-87 JESD51-2 MPC561 MPC563 EPEE11 F63 CAPACITOR
Contextual Info: APPENDIX F ELECTRICAL CHARACTERISTICS This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing characteristics of the MPC561 / MPC563. The MPC561 / MPC563 is designed to operate at 40 MHz, or optionally up to 56 MHz.

D1911

Abstract: 10INTERRUPT circuit diagram of MOD 100 counter using ic 7490 GDDR5 pcb layout motorola ic MC 1435 op amp MPC555 MPC561 MPC563 Three-Five Systems 555 timer 38 khz square wave generator
Contextual Info: MPC561/3RM/D MPC561/MPC562 / MPC563/MPC564 REFERENCE MANUAL Revised 29 June 2001  Copyright 2001 MOTOROLA; All Rights Reserved MPC561/3RM/D MPC561/MPC562 / MPC563/MPC564 REFERENCE MANUAL Revised 29 June 2001  Copyright 2001 MOTOROLA; All Rights Reserved

pal 011 A SPEAKER OUTPUT IC

Abstract: STV2116 STV2116A STV2116 pin out STV2118B pal 012 A SPEAKER OUTPUT IC h431 transistor
Contextual Info: ^ 7 SGS-THOMSON h7 £ S TV 2116A BUS CONTROLLED PAL/NTSC TV PROCESSOR PRO DU CT PREVIEW • ■ ■ ■ ■ ■ ■ ■ ■ ■ l2C BUS CONTROL OF ALL FUNCTIONS INTEGRATED FILTERS TRAP, BANDPASS INTEGRATED LUMINANCE DELAY LINE PALVNTSCCHROMA DEMODULATORS