LOGIC GATES PIN CONFIGURATION AND Search Results

plhs18p8

Contextual Info: Signetics PLHS18P8A Programmable AND Array Logic 18x72x8 Military Standard Products Product Specification PIN CONFIGURATION DESCRIPTION FEATURES The PLHS18P8A is a two-level logic ele­ ment consisting of 72 AND gates and 8 OR gates with fusible connections for pro­

Contextual Info: MITSUBISHI ASTTLs M74AS08P QUADRUPLE 2-INPUT POSITIVE AND GATE DESCRIPTION PIN CONFIGURATION TOP VIEW The M74AS08P is a semiconductor integrated circuit consisting of four 2-input positive-logic AND gates, us­ able as negative-logic OR gates. FEATURES • High speed

logic gates pin configuration

Abstract: PLHS18P8A pin configuration of logic gates logic gates pin configuration and
Contextual Info: Product specification Signetics Military Standard Products Programmable AND array logic 18 x 72 x 8 PIN CONFIGURATION DESCRIPTION FEATURES The PLHS18P8A is a two-level logic element consisting of 72 AND gates and 8 OR gates with fusible connections for programming I/O

74AS1804

Contextual Info: MITSUBISHI ASTTLs -*00°° M 74AS1804P HEX 2-INPUT NAND DRIVER DESCRIPTION The M74AS1804P is a semiconductor integrated circuit consisting of six 2-input positive-logic NAND buffer gates, usable as negative-logic NOR buffer gates. PIN CONFIGURATION TOP VIEW

Contextual Info: MITSUBISHI ASTTLs pS?< M74AS20P DUAL 4 -INPUT POSITIVE NAND G ATE DESCRIPTION PIN CONFIGURATION TOP VIEW The M74AS20P is a semiconductor integrated circuit consisting of two 4-input positive-logic NAND gates, us­ able as negative-logic NOR gates. FEATURES

M74AS02P

Contextual Info: MITSUBISHI ASTTLs M74AS02P ŸŸ& 0 QUADRUPLE 2-INPUT POSITIVE NOR GATE DESCRIPTION PIN CONFIGURATION TOP VIEW The M74AS02P is a semiconductor integrated circuit consisting of four 2-input positive-logic NOR gates, us­ able as negative-logic NAND gates.

74AS1000

Contextual Info: MITSUBISHI A STTLs M 74AS1000AP QUADRUPLE 2-INPUT POSITIVE NAND DRIVER DESCRIPTION PIN CONFIGURATION TOP VIEW The M74AS1000AP is a semiconductor integrated circuit consisting of four 2-input positive-logic NAND buffer gates, usable as negative-logic NOR buffer gates.

Contextual Info: Signetics 82S153A PLS153A Field Programmable Logic Array (18x42x10) Military Customer Specific Products Signetics Programmable Logic Product Specification PIN CONFIGURATION DESCRIPTION FEATURES The 82S153A is a two-level logic element, consisting of 42 A N D gates and 10 O R

26 SIGNETICS

Contextual Info: S ig n e t ic s PLS173 Field-Programmable Logic Array 22x42x10 Military Application Specific Products Slgnetlcs Programmable Logic Product Specification PIN CONFIGURATION DESCRIPTION FEATURES The PLS173 is a two-level logic element consisting of 42 AND gates and 10 OR

74LS18P

Contextual Info: MITSUBISHI LSTTLs M 74LS 18P DUAL 4-IN P U T NAND SCHMITT TRIGGER DESCRIPTION The M 74LS 18P is a semiconductor integrated circuit PIN CONFIGURATION TOP VIEW containing tw o 4-input positive-logic N A N D gates having a schm itt trigger function and negative-logic N O R gates.

Dual 4-input NAND Schmitt Trigger

Abstract: M74LS13P M74ls14p 20-PIN
Contextual Info: MITSUBISHI LSTTLs M74LS13P DUAL 4 -IN P U T NAND S C H M ITT TRIGGER DESCRIPTION The M 74LS 13P PIN CONFIGURATION TOP VIEW is a semiconductor integrated circuit containing tw o 4-inp ut positive-logic N A N D gates having a Schm itt trigger function and negative-logic NOR gates.

Contextual Info: MITSUBISHI LSTTLs M74LS13P DUAL 4 -IN P U T NAND S C H M ITT TRIGGER DESCRIPTION The M 74LS 13P PIN CONFIGURATION TOP VIEW is a semiconductor integrated circuit containing tw o 4-inp ut positive-logic N A N D gates having a Schm itt trigger function and negative-logic NOR gates.

74ls20 mitsubishi

Contextual Info: MITSUBISHI HIGH S P E E D CMOS M74HC20P/FP/DP DUAL 4-INPUT P O S IT IV E NAND GATE DESCRIPTION The M74HC20 is a semiconductor integrated circuit con­ sisting of two 4-input positive-logic NAND gates, usable as negative-logic NOR gates. PIN CONFIGURATION TOP VIEW

Contextual Info: GD54/74S08 QUADRUPLE 2-INPUT POSITIVE AND GATES Description Pin Configuration This device contains four independent 2-input AND gates. It performs the Boolean functions Y = A » B or Y = A + B in positive logic. Function Tabie each gate INPUT A O U T PU T

Contextual Info: PLS173 Slgnetics Field-Programmable Logic Array 22x42x10 Military Application Specific Products Signetics Programmable Logic Product Specification PIN CONFIGURATION DESCRIPTION FEATURES T h e P L S 1 7 3 is a two-level logic elem ent consisting of 4 2 A N D gates and 10 O R

plhs18p8

Abstract: PLHS18 PLHS18P8A
Contextual Info: Signetics Military Standard Products PLHS18P8A Programmable AND Array Logic 18x72x8 Product Specification PIN CONFIGURATION DESCRIPTION FE A TU R E S The PLHS18P8A is a two-level logic ele­ ment consisting of 72 ANDgates and SOR gates with fusible connections for pro­

Contextual Info: MITSUBISHI ASTTLs M74AS1808P HEX 2-IN PU T AND DRIVER DESCRIPTION The M 7 4A S 1 808 P is a sem iconductor integrated circuit PIN CONFIGURATION TOP VIEW consisting of six 2-input positive-logic A N D buffer gates, usable as n egative-log ic OR buffer gates.

Contextual Info: MITSUBISHI ASTTLs M 74AS1008AP QUADRUPLE 2-INPUT POSITIVE AND DRIVER DESCRIPTION PIN CONFIGURATION TOP VIEW The M 7 4A S 1 008 A P is a sem iconductor integrated circuit consisting of four 2-input positive-logic AND buffer gates, usable as n e g ative-log ic OR buffer gates.

Contextual Info: GD54/74S51 DUAL 2-WIDE 2-INPUT AND-OR-INVERT GATES Description Pin Configuration This device contains two independent combinations of gates each of which performs the logic AND-ORINVERT function. MAKE N O EXTERNAL CO NNECTIO N V Cc 1B 1D 1C 1Y Y=AB+C D Function Table

Contextual Info: MITSUBISHI ASTTLs M74AS21P i DUAL 4 -INPUT POSITIVE AND GATE DESCRIPTION T he PIN CONFIGURATION TOP VIEW M 74A S 21P is a sem iconductor integrated circuit consisting of two 4-inp ut positive-logic A N D gates, us­ ab le as n egative-log ic OR gates. FEATURES

Contextual Info: GD54/74LS09 QUADRUPLE 2-INPUT POSITIVE AND GATES WITH OPEN-COLLECTOR OUTPUTS Description Pin Configuration This d evice contains four ind epen den t 2-input AND gates. It performs the Boolean functions Y = A • B or Y = A + B in positive logic. T h e open-collector out­

Contextual Info: GD54/74LS15 TRIPLE 3-INPUT POSITIVE AND GATES WITH OPEN-COLLECTOR OUTPUTS Description Pin Configuration This d evice contains th ree ind epen den t gates each of w hich perform s the logic AND function. Y = A B C T he o p en-collector outputs require external pull-up

Contextual Info: MITSUBISHI ASTTLs M74AS832BP HEX 2-IN PU T OR DRIVER DESCRIPTION The M 74A S 832B P is a sem iconductor integrated circuit PIN CONFIGURATION TOP VIEW consisting of six 2-input positive-logic OR buffer gates, usable as negative-log ic A N D buffer gates.

Contextual Info: GD54/74LS02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES Description Pin Configuration This device contains four independent 2-input NOR gates. It performs the Boolean functions Y = A B or Y = A + B in positive logic. VCc 4Y 4B 4A 3Y 3B 3A Function Table INPUTS OUTPUT