LOGIC GATES CIRCUIT DIAGRAM Search Results

74AS1804

Contextual Info: MITSUBISHI ASTTLs -*00°° M 74AS1804P HEX 2-INPUT NAND DRIVER DESCRIPTION The M74AS1804P is a semiconductor integrated circuit consisting of six 2-input positive-logic NAND buffer gates, usable as negative-logic NOR buffer gates. PIN CONFIGURATION TOP VIEW

M74AS02P

Contextual Info: MITSUBISHI ASTTLs M74AS02P ŸŸ& 0 QUADRUPLE 2-INPUT POSITIVE NOR GATE DESCRIPTION PIN CONFIGURATION TOP VIEW The M74AS02P is a semiconductor integrated circuit consisting of four 2-input positive-logic NOR gates, us­ able as negative-logic NAND gates.

74LS132P

Abstract: M74LS14P
Contextual Info: MITSUBISHI LSTTLs M74LS132P QUADRUPLE 2-IN P U T PO SITIVE NAND SCHM ITT TRIGGER DESCRIPTION The M74LS132P is a semiconductor integrated circuit containing four 2-input positive-logic NAND gates having a Schmitt trigger function and negative-logic NOR gates.

Contextual Info: MITSUBISHI ASTTLs pS?< M74AS20P DUAL 4 -INPUT POSITIVE NAND G ATE DESCRIPTION PIN CONFIGURATION TOP VIEW The M74AS20P is a semiconductor integrated circuit consisting of two 4-input positive-logic NAND gates, us­ able as negative-logic NOR gates. FEATURES

74AS1000

Contextual Info: MITSUBISHI A STTLs M 74AS1000AP QUADRUPLE 2-INPUT POSITIVE NAND DRIVER DESCRIPTION PIN CONFIGURATION TOP VIEW The M74AS1000AP is a semiconductor integrated circuit consisting of four 2-input positive-logic NAND buffer gates, usable as negative-logic NOR buffer gates.

Contextual Info: MITSUBISHI ASTTLs M74AS08P QUADRUPLE 2-INPUT POSITIVE AND GATE DESCRIPTION PIN CONFIGURATION TOP VIEW The M74AS08P is a semiconductor integrated circuit consisting of four 2-input positive-logic AND gates, us­ able as negative-logic OR gates. FEATURES • High speed

spckt_10003.0

Contextual Info: Category: Special Circuits CIRCUIT IDEAS FOR DESIGNERS Schematic no. SPCKT_10003.0 0.2V Supply Voltage Nanopower Two-Input NOR and NAND gates Description Simple logic gates such as NOR and NAND gates can be readily implemented using EPAD MOSFETs to operate

74LS00P

Abstract: M74LS00P
Contextual Info: M IT S U B IS H I LSTTLs M74LS00P QUADRUPLE 2-IN P U T POSITIVE NAND GATES DESCRIPTION The M 74LS 00P is semiconductor integrated circuit contain­ ing fo u r dual-input positive-logic N A N D gates, usable as negative-logic N O R gates. FEATURES • High breakdown input voltage V | S 15 V

M74LS00P

Abstract: 20-PIN M74LS00
Contextual Info: M IT S U B IS H I LSTTLs M74LS00P QUADRUPLE 2-IN P U T POSITIVE NAND GATES DESCRIPTION The M 74LS 00P is semiconductor integrated circuit contain­ ing fo u r dual-input positive-logic N A N D gates, usable as negative-logic N O R gates. FEATURES • High breakdown input voltage V | S 15 V

IC TTL 74LS00

Abstract: 74ls00 74LS00 gate diagram
Contextual Info: MITSUBISHI HIGH SPEED CMOS M74HCT00P/FP/DP QUADRUPLE 2-INPUT POSITIVE NAND GATE WITH L S TTL-C O M P A TIB LE INPUTS DESCRIPTION The M74HCT00P is a semiconductor integrated circuit con­ sisting of four 2-input positive-logic NAND gates, usable as negative-logic NOR gates.

74ls20 mitsubishi

Contextual Info: MITSUBISHI HIGH S P E E D CMOS M74HC20P/FP/DP DUAL 4-INPUT P O S IT IV E NAND GATE DESCRIPTION The M74HC20 is a semiconductor integrated circuit con­ sisting of two 4-input positive-logic NAND gates, usable as negative-logic NOR gates. PIN CONFIGURATION TOP VIEW

74LS18P

Contextual Info: MITSUBISHI LSTTLs M 74LS 18P DUAL 4-IN P U T NAND SCHMITT TRIGGER DESCRIPTION The M 74LS 18P is a semiconductor integrated circuit PIN CONFIGURATION TOP VIEW containing tw o 4-input positive-logic N A N D gates having a schm itt trigger function and negative-logic N O R gates.

TC4081BP

Abstract: DIP14-P-300-2 TC4081B TC4081BF TC4081BFN
Contextual Info: TC4081BP/BF/BFN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC4081BP,TC4081BF,TC4081BFN TC4081B Quad 2-Input AND Gate TC4081B is positive logic AND gates with two inputs respectively. Since all the outputs of these gates are equipped with the

tc4081bp

Contextual Info: TC4081BP/BF/BFN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC4081BP,TC4081BF,TC4081BFN TC4081B Quad 2-Input AND Gate TC4081B is positive logic AND gates with two inputs respectively. Since all the outputs of these gates are equipped with the

TC4081BP

Contextual Info: TC4081BP/BF/BFN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC4081BP,TC4081BF,TC4081BFN TC4081B Quad 2-Input AND Gate TC4081B is positive logic AND gates with two inputs respectively. Since all the outputs of these gates are equipped with the

Contextual Info: MITSUBISHI LSTTLs M74LS13P DUAL 4 -IN P U T NAND S C H M ITT TRIGGER DESCRIPTION The M 74LS 13P PIN CONFIGURATION TOP VIEW is a semiconductor integrated circuit containing tw o 4-inp ut positive-logic N A N D gates having a Schm itt trigger function and negative-logic NOR gates.

TC4081BP

Abstract: DIP14-P-300-2 TC4081B TC4081BF TC4081BFN
Contextual Info: TC4081BP/BF/BFN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC4081BP,TC4081BF,TC4081BFN TC4081B Quad 2-Input AND Gate TC4081B is positive logic AND gates with two inputs respectively. Since all the outputs of these gates are equipped with the

Contextual Info: TC4081BP/BF/BFN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC4081BP,TC4081BF,TC4081BFN TC4081B Quad 2-Input AND Gate TC4081B is positive logic AND gates with two inputs respectively. Since all the outputs of these gates are equipped with the

EP1810JC-35

Abstract: programming manual EP910 EP1810LC-35 OLC-45 EP1810JC35 programming manual EPLD EP1810LI-45 EP1810JC EP1810I Erasable Programmable Logic Device
Contextual Info: EP1810 HIGH-PERFORMANCE 48-MACROCELL ERASABLE PROGRAMMABLE LOGIC DEVICE EPLD D3232. FEBHUARY 1989-REVISED AUGUST 1989 CHIP-CARRIER PACKAGE Erasable, U ser-Configurable LSI Circuit C apable of Implementing 2100 Equivalent Gates of Conventional and Custom Logic

Contextual Info: TC4071BFN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC4071BFN TC4071B Quad 2-Input OR Gate TC4071B is positive logic OR gates with two inputs respectively. As all the outputs of gates are equipped with the buffer circuits of inverters, the input/output propagation

DM7400

Abstract: DM7400M DM7400N M14A MS-001 N14A
Contextual Info: Revised July 2001 DM7400 Quad 2-Input NAND Gates General Description This device contains four independent gates each of which performs the logic NAND function. Ordering Code: Order Number Package Number DM7400M M14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, 0.150" Narrow

Contextual Info: TC4081BFN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC4081BFN TC4081B Quad 2-Input AND Gate TC4081B is positive logic AND gates with two inputs respectively. Since all the outputs of these gates are equipped with the buffer circuits of inverters, the input/output propagation

DM74LS04

Abstract: DM74LS04 HEX INVERTING GATES DM74LS04N DM74LS04M DM74LS04SJ M14A M14D MS-001 N14A
Contextual Info: Revised March 2000 DM74LS04 Hex Inverting Gates General Description This device contains six independent gates each of which performs the logic INVERT function. Ordering Code: Order Number Package Number Package Description DM74LS04M M14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-120, 0.150 Narrow

Contextual Info: TC4071BP/BF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC4071BP,TC4071BF TC4071B Quad 2-Input OR Gate TC4071B is positive logic OR gates with two inputs respectively. As all the outputs of gates are equipped with the buffer circuits of inverters, the input/output propagation