1K x 4 static ram ttl
Abstract: lh5114
Contextual Info: LH5114 CMOS 4K 1K 4 Static RAM x DESCRIPTION FEATURES • 1,024 x 4 bit organization • Access tim e: • Power consumption: The LH5114H is a static RAM organized as 1,024 4 bits. It is fabricated using silicon-gate CMOS proc ess technology. x 150 ns (MAX.)
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lh5114lh5114h18-pin300-mil+314h-3lh5114h-151k x 4 static ram ttl
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LH5114H15
Abstract: lh5114 1K x 8 static ram LH5114H 1K x 4 static ram ttl 1k x 4
Contextual Info: LH5114 CMOS 4K 1K x 4 S ta tic RAM FEATURES DESCRIPTION • 1,024 x 4 bit organization The LH5114H is a static RAM organized as 1,024 x 4 bits. It is fabricated using silicon-gate CMOS proc ess technology. • Access time: 150 ns (MAX.) • Power consumption:
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lh511418-pin300-millh5114h+720-pin5114h-3lh5114h-15lh5114h151k x 8 static ram1k x 4 static ram ttl1k x 4
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LH5114
Abstract: LH5114H15 LH5114H
Contextual Info: blE D SHARP CORP • Ô1Û07TÔ GODTbVe llâ « S R P J LH5114 FEATURES • 1,024 • Access time: 150 ns MAX. • Power consumption: Operating: 20 mA (MAX.) Standby: 5 nA (MAX.) x 4 bit organization CMOS 4K (1K x 4) Static RAM DESCRIPTION The LH5114H is a static RAM organized as 1,024
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lh5114lh5114h18-pin300-mil+428-pin5114h3lh5114h-15lh5114h15
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lh5114l
Abstract: SHARP EL
Contextual Info: SHARP EL E K / MELEC O IV 1SE 0 | 31507^0 O O O Q Ì'n s | C M O S 4096-Bit Static Random Access Memory LH5114L T -4 6 -2 3 -ÌZ LH5114L CMOS 4096-Bit Static Random Access Memory Pin Connections Description The L H 5114L is a static RAM organized as 1 ,0 2 4 X 4 bit by using silicon-gata CMOS process
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lh5114l4096-bit5114lflla07tfl+524dip24typ-62typ54typ-sharp el
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sn76131
Abstract: tlo72cp TOSHIBA 2N3055 M53207P 2N3055 TOSHIBA KIA7313AP kia7640ap LA5530 M5L8155P TBB1458B
Contextual Info: ACTIVE ELECTRONICS COMPONENTS CROSS REFERENCE GUIDE 2SC429GTM 2SC458 2SC458LG 2SC503 2SC504 2SC510 2SC512 2SC519 2SC520A 2SC594 2SC699A 2SC780 2SC809-1 2SC945 2SC3012 2SC3074 2SC3114 2SC3115 2SC3116 2SC3117 2SC3134 2SC3135 2SC3138 2SC3143 2SC3144 2SC3145 2SC3157
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2sc429gtm2sc4582sc458lg2sc503+162sc5042sc5102sc5122sc5192sc520a2sc594sn76131tlo72cptoshiba 2n3055m53207p2n3055 toshibakia7313apkia7640apla5530m5l8155ptbb1458b
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TC5513APL-20
Abstract: TC5514P TC5513AP-20 Srm2114 MSM5114-2RS tc5513apl TC5513AP LH5114-6 MWS5114-2 P4C148-15
Contextual Info: 30 - 4 K X ÎSÂÏEK a & í± £ CC TAAC •ax ns) TCAC max (ns) TOE ■ax (ns) -i 7 CMOS f > TOH min (ns) TOD max (ns) / TVfP S t a t i c Í? RAM ft ( 1 0 2 4 X 4 ) 18 P I N A € TDH (ns) TDS min (ns) (ns) TSD min (ns) T*R max (ns) V D D or V C C (V) I DD
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024x4lh5114-6m5891p-30m5891p-45+14tc5513apl-20tc5514ap/jtc5514ap/d-2tc5514ap/d-3tc5514p-1tc5514p-2tc5514ptc5513ap-20srm2114msm5114-2rstc5513apltc5513apmws5114-2p4c148-15
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LH5114-4
Abstract: 7779A LR48106
Contextual Info: SHARP LR48106 LR4 8 1 0 6 Pulse/Tone Dialer LSI with LCD Driver DESCRIPTION The LR48106 is a CMOS pulse/tone dialer LSI which has a 12-digit LCD driver and a clock func tion. Used in combination with an external RAM, it provides a 32-digit x 34-channel auto-dialing
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lr4810612-digit32-digit34-channel+3lh5114lh5114-47779a
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LA 7376
Abstract: Mem 5116 LJ sharp EL display DTMF circuit LR48106
Contextual Info: Pulse/Tone D ialer LSI with LC D Driver LR48106 LR 48106 Pulse/Tone Dialer LSI with LCD < 1 • ■ Description 1. Key or switch input allows switching from pulse to tone mode to provide mixed dialing capability 2. Pulse rate : 10/20pps pin-selectable 3. Make ratio : 33/40% pin-selectable
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lr4810612-digit32-digitx34-channel32digit+710/20ppslh511432-digitla 7376mem 5116lj sharp el displaydtmf circuit
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LH5160N
Abstract: LH5115 LH5118D LH5160 LH5160D LH521000 LH5167 LH52252A LH5114H LH5911-55
Contextual Info: NOV 0 5 1990 L H 5 9 1 1 /L H 5 9 1 2 /L H 5 9 1 4 2K x 8 CMOS Dual Port RAM Preliminary Data Sheet Features Functional Description The IH 5911, LH5912 and LH5914are dual port static RAMs that use true dual port memory cells to allow each port to independently access any location in memory.
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lh5912lh5914arelh5911lh5914+13/idt713416kx1864kx18lh5160nlh5115lh5118dlh5160lh5160dlh521000lh5167lh52252alh5114hlh5911-55
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LH5911
Abstract: lh5167-55 LH5101 LH52250 LH5160D LH5167 LH52252 LH5114H lh5160n 4kx8 static ram ttl
Contextual Info: NOV 0 5 1990 L H 5 9 1 1 /L H 5 9 1 2 /L H 5 9 1 4 2K x 8 CMOS Dual Port RAM Preliminary Data Sheet Functional Description Features The LH5911. LH5912 and LH5914are dual port static RAMs that use true dual port memory cells to allow each port to independently access any location in memory.
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lh5911/lh5912/lh5914lh5912lh5914are+12lh591416kx18lh52270lh5167-55lh5101lh52250lh5160dlh5167lh52252lh5114hlh5160n4kx8 static ram ttl
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LR3441
Abstract: marking code B9 DG SMD Transistor transistor smd sensor 80L transistor bf 175 sdz-370n ccd LZ1032 Transister Data Book
Contextual Info: MOS DATA BOOK General Information Gate Arrays/Standard Cells Display Drivers 3 J T elecommunications II CCDs/CCD Peripherals ICs for Audio/Visual Equipment 6 | Voice/Melody Generators ICs for Clock Others Preface In recent years, the seemingly unlimited progress seen in
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lh5047/lh5048lr3441marking code b9 dg smd transistortransistor smd sensor 80l+4transistor bf 175sdz-370n ccdlz1032transister data book
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LC3514AL-15
Abstract: AM9124 HM6148P-6 m911 CY7C148-25 CY7C148-35 CY7C149-35 CY7C149-45 F2114 F2114-2
Contextual Info: - 24 4 K 7. ít £ Ci Am9114B TAAC max (ns TCAC (ns) TOE max (ns) \ n M 0 S ••/ S t a t i c > TOH rain (ns) TOD max (ns) RAM ft. TWP min (ns) TDS min (ns) 200 200 ( 1 0 2 4 x 4 ) TDH min (ns) T*D min (ns) TWR V D D or V C C (ns) (V) 18 P I N A it?: m
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1024x4am9114bam9114c9114e+15ims1223p/s-45lc3514a-15lc3514a-20lc3514al-15lc3514ai-20ih5114-4am9124hm6148p-6m911cy7c148-25cy7c148-35cy7c149-35cy7c149-45f2114f2114-2
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LC3514AL-15
Abstract: HM6148P HM6148LP HM6148P-6 CY2149-35 CY2149-45 LC3514AL15 CY7C148-25 CY7C148-35 CY7C149-25
Contextual Info: - 4 K X m z, it £ C O TAAC max ris TCAC wax (ns) TO E max (ns) A -y TOH min (ns) CMOS y * ? TO D wax (ns) TW P min (ns) S t a t i c 1Í TDS lin (ns) R A M (1 0 2 4 x 4 ) m tí TD H min (ns) T iD min (ns) TWR max (ns) VDD o r VCC (V) ID D max (mA) 5514 1 8 P 1 N
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024x418p1ncy7c148-25cy7c148-35+12cy7c148-45cy7c149-25ims1223p/s-45lc3514a-15lc3514a-20lc3514al-15hm6148phm6148lphm6148p-6cy2149-35cy2149-45lc3514al15
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TC5513APL-20
Abstract: TC5514P TC5513AP-20 srm2114 SRM2114C HM6147 HM6147-3 HM6147LP tc5513apl TC5513APL20
Contextual Info: 19 4 K CMOS 7, 'i m & tt « CC TAAC max ns) TCAC max (ns) TOF max (ns) •f- TOH rain (ns) TOD max (ns) y ? TWP (ns) S tatic R A M (4 0 9 6 x 1) % 14 # TPS min (ns) TDH min (ns) TWD rain (ns) TWR max (ns) V D D or V C C (V) I8PÍN À if I DD max (mA) CY7C147-25
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cy7c147-25cy7c147-35cy7c147-45hm6147+14tc5513apl-20tc5514ap/jtc5514ap/d-2tc5514ap/d-3tc5514p-1tc5514p-2tc5514ptc5513ap-20srm2114srm2114chm6147-3hm6147lptc5513apltc5513apl20
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