LFBGA 12X12 Search Results

Contextual Info: 32-Channel 14-Bit Voltage-OutputDAC AD5532-1/AD5532-2/AD5532-3 ANALOG ► DEVICES Preliminary Technical Data FEATURES High Integration: 32-channel DAC in 12x12 mm2 LFBGA Adjustable Voltage Output Range Guaranteed Monotonie Readback capability SPI Serial Interface

1000bs

Contextual Info: a 32-Channel 14-Bit Voltage-Output DAC AD5532* Preliminary Technical Data FEATURES High Integration: 32-channel DAC in 12x12 mm2 LFBGA Adjustable Voltage Output Range Guaranteed Monotonic Readback capability DSP-/Microcontroller-Compatible Serial Interface

dac interfacing with 8051 microcontroller

Abstract: 8051 Family with internal ADC dac commax A0553 AD5532-3 circuit diagram for interfacing dac with 8051 AD5532 AD5532-1 AD5532-2 AD5532-5
Contextual Info: ► ANALOG DEVICES 32-Channel 14-Bit Voltage-Output DAC PreliminaryTechnical Data FEATURES High Integration: 32-channel DAC in 12x12 mm2 LFBGA Adjustable Voltage Output Range Guaranteed Monotonic Readback capability DSP-/Microcontroller-Compatible Serial Interface

AD5517

Abstract: AD5517-1 AD5517-2 AD5517-3
Contextual Info: PRELIMINARY TECHNICAL DATA a 16-Channel 14-Bit Voltage-Output DAC AD5517-1/AD5517-2/AD5517-3* Preliminary Technical Data FEATURES High Integration: 16-channel DAC in 12x12 mm 2 LFBGA Guaranteed Monotonic Low Power, SPI TM, MICROWIRETM and DSP-Compatible 3-Wire Serial Interface

AD5516

Abstract: AD5516-1 AD5516-2 AD5516-3 BC74
Contextual Info: PRELIMINARY TECHNICAL DATA a 16-Channel 12-Bit Voltage-Output DAC AD5516-1/AD5516-2/AD5516-3* Preliminary Technical Data FEATURES High Integration: 16-channel DAC in 12x12 mm 2 LFBGA Guaranteed Monotonic Low Power, SPI TM, MICROWIRETM and DSP-Compatible 3-Wire Serial Interface

PIC16C6

Abstract: 1000bs
Contextual Info: a 32-Channel Infinite Sample-and-Hold AD5533* Preliminary Technical Data FEATURES Infinite Sample & Hold Capability to ±0.012% accuracy High Integration: 32-channel SHA in 12x12 mm2 LFBGA µ s max Per channel acquisition time of 16µ Adjustable Voltage Output Range

1000bs

Abstract: AD5532-2 AD5532 AD5532-1 AD5532-3 AD5532ABC-1 AD5532ABC-2 AD780
Contextual Info: a 32-Channel 14-Bit Voltage-Output DAC AD5532-1/AD5532-2/AD5532-3 Preliminary Technical Data FEATURES High Integration: 32-channel DAC in 12x12 mm2 LFBGA Adjustable Voltage Output Range Guaranteed Monotonic Readback capability SPI Serial Interface Ω AD5532-1, AD5532-2

AD5532-2

Abstract: AD5532 AD5532-4 AD5532-5 AD5532ABC-1 AD5532ABC-2 AD5532ABC-5 AD780
Contextual Info: a 32-Channel Infinite Sample-and-Hold AD5532-4/AD5532-5 Preliminary Technical Data GENERAL DESCRIPTION The AD5532 combines a 32 channel voltage translation function with an infinite output hold capability. An analog input voltage on the common input pin, VIN, is

MX29GL256

Abstract: 28F512P30 Numonyx M29W256G 28F00AP30 w25q128 MX25L6445 28F00AM29EW M29DW127G 28F128P30 PF38F3040M0Y3D
Contextual Info: Spansion NOR Flash Memory Competitive Cross Reference Guide December 2009 Parallel 1.8V Density Voltage Bus Mb (V) VIO (V) Type Bus Sector Width Type # Initial Access Burst Speed Banks Times (ns) (MHz) Packages Temp Range Recommended Pin Software Spansion OPN Compatible Compatible Notes

Contextual Info: STA680 HD Radio baseband receiver Datasheet − production data Features • IBOC in-band on-channel digital audio broadcast signal decoding for AM/FM hybrid and all-digital modes ■ Dual-channel HD 1.5 for background scanning and data services ■ HD codec (HDC) audio decompression

TDA7528

Abstract: STA3004 Xtensa HiFi 2 Audio Engine AM FM TUNER module car 168-ball E1 AUDIO CONVERTER Xtensa LQFP144 STA680 STA680Q
Contextual Info: STA680 HD Radio base-band receiver Preliminary Data Features General • HD Radio signal decoding for AM and FM digital audio ■ Tensilica™ signal/audio processing core architecture running up to 166 MHz ■ Hardware support for conditional access one-time programmable 640-bit memory

STA3004

Abstract: TDA7528 AC00720 STA680 Mp3/wma decoder i2s Xtensa LQFP144 STA680Q iboc
Contextual Info: STA680 HD Radio baseband receiver Preliminary Data Features General • HD Radio signal decoding for AM and FM digital audio ■ Tensilica™ signal/audio processing core architecture running up to 166 MHz ■ Hardware support for conditional access one-time programmable 640-bit memory

tda7706

Abstract: TDA770 RF TDA7706 Xtensa STA680 tda77 CORE i3 ARCHITECTURE Tuner ts pinout 224MHZ Xtensa HiFi 2 Audio Engine
Contextual Info: STA680 HD Radio baseband receiver Features • IBOC in-band on-channel digital audio broadcast signal decoding for AM/FM hybrid and all-digital modes ■ Dual-channel HD 1.5 for background scanning and data services ■ HD codec (HDC) audio decompression

HLQFP 176 Package

Abstract: FBGA Package 14x14 121 bga 10x10 BGA 27X27 pitch 23X23 lfbga 12X12 1.0/Daewon BGA 7x7 hssop TQFP 14X20 TSOP 14X20
Contextual Info: IC Package Line-up As of July, 2009 ● : In mass production ○ : Under development Package name DIP SDIP Package dimensions mm mil 6.3x8.84 (300) 6.3x9.6 (300) 6.3x19 (300) 6.3x19.2 (300) 6.3x24.5 (300) 13.4x35.6 (600) 6.3x19 (300) 8.9x28 (400) 13x36.72 (600)

tda7706

Abstract: TDA770 iboc STA680Q 0101111B ax 2008 lqfp 48 Xtensa AEC-Q100 LQFP144 STA680
Contextual Info: STA680 HD Radio baseband receiver Features • IBOC in-band on-channel digital audio broadcast signal decoding for AM/FM hybrid and all-digital modes ■ Dual-channel HD 1.5 for background scanning and data services ■ HD codec (HDC) audio decompression

TDA7528

Abstract: STA680Q Xtensa AM FM TUNER module car STA680 HD radio LQFP144 STA3004 MMC spi circuit diagram of 9.2 surround sound
Contextual Info: STA680 HD Radio baseband receiver Preliminary data Features General • HD Radio signal decoding for AM and FM digital audio ■ Tensilica™ signal/audio processing core architecture running up to 166 MHz ■ Hardware support for conditional access one-time programmable 640-bit memory

tda7706

Abstract: TDA770 tda77 Xtensa HiFi 2 Audio Engine ffts used in software defined radio stmicroelectronics Serial Flash Memory Device 74418 iboc 3v3 regulator STMicroelectronics sdra12
Contextual Info: STA680 HD Radio baseband receiver Datasheet − production data Features • IBOC in-band on-channel digital audio broadcast signal decoding for AM/FM hybrid and all-digital modes ■ Dual-channel HD 1.5 for background scanning and data services ■ HD codec (HDC) audio decompression

TDA7706

Contextual Info: STA680 HD Radio baseband receiver Datasheet - production data • IIS serial audio interface with programmable sample rate converter  Primary and secondary serial interfaces for based on industry standard IIC and SPI  Several General purpose IOs '!0'03

Contextual Info: Product: PCI Express Octal UART I/O Bridge Part Numbers: PI7C9X7958 Product Description The PI7C9X7958 is a PCI Express Octal UART Universal Asynchronous Receiver-Transmitters I/O Bridge. It is specifically designed to meet the latest system requirements

Contextual Info: STA680 HD Radio baseband receiver Datasheet  production data Features • IBOC in-band on-channel digital audio broadcast signal decoding for AM/FM hybrid and all-digital modes ■ Dual-channel HD 1.5 for background scanning and data services ■ HD codec (HDC) audio decompression

PI7C9X7958

Abstract: 16C950 PI7C9X7958ANB PI7C9X7958ANBE ofRS232 uart 16c950
Contextual Info: Product: PCI Express Octal UART I/O Bridge Part Numbers: PI7C9X7958 Product Description ® The PI7C9X7958 is a PCI Express Octal UART Universal Asynchronous Receiver-Transmitters I/O Bridge. It is specifically designed to meet the latest system requirements

TDA7706

Abstract: TDA770 Xtensa HiFi 2 Audio Engine 12x12mm BGA package thermal resistance TDA77 module tuner fm RF TDA7706
Contextual Info: STA680 HD Radio baseband receiver Datasheet − production data Features • IBOC in-band on-channel digital audio broadcast signal decoding for AM/FM hybrid and all-digital modes ■ Dual-channel HD 1.5 for background scanning and data services ■ HD codec (HDC) audio decompression

AT91CAP7S

Abstract: 176TFBGA 176-TFBGA 225-LFBGA 144-LFBGA
Contextual Info: Features • Incorporates the ARM7TDMI ARM® Thumb® Processor • • • • • • • • • • • • • – 80 MIPS at 80MHz – EmbeddedICE In-circuit Emulation, Debug Communication Channel Support Additional Embedded Memories – One 256 Kbyte Internal ROM, Single-cycle Access at Maximum Matrix Speed

AT91CAP7

Abstract: AT91CAP7A a1358 20x20x14
Contextual Info: Features • Incorporates the ARM7TDMI ARM® Thumb® Processor • • • • • • • • • • • • • – 72 MIPS at 80MHz – EmbeddedICE In-circuit Emulation, Debug Communication Channel Support Additional Embedded Memories – One 256 Kbyte Internal ROM, Single-cycle Access at Maximum Matrix Speed