LDPC DECODER TIMING Search Results

LDPC DECODER TIMING Result Highlights (5)

Part	Manufacturer	Description	Download
AM27S25DM	Rochester Electronics LLC	AM27S25 - OTP ROM	PDF
54LS154F/883C	Rochester Electronics LLC	54LS154 - 4-Line to 16-Line Decoder/Demultiplexer	PDF
27S185ADM/B	Rochester Electronics LLC	27S185A - OTP ROM, 2KX4	PDF
27S185ALM/B	Rochester Electronics LLC	27S185A - OTP ROM, 2KX4	PDF
54LS156/BEA	Rochester Electronics LLC	54LS156 - Decoder, Dual 2-To-4-Line, With Open-Collector - Dual marked (M38510/32602BEA)	PDF

LDPC DECODER TIMING Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
STV0910 Abstract: demodulator dvb-s2 vcm 16APSK LFBGA-168 DVB-S2 integrated receiver demodulator DVB-S2 32APSK DVB-S2 demodulator VCM DVB-S2 demodulator demodulator equalizer Contextual Info: STV0910 Multi-standard advanced dual demodulator for satellite digital TV broadcast set-top boxes Data brief Features • Dual multi-standard demodulation for broadcast applications – DVBS2 QPSK, 8PSK, CCM, VCM – Legacy DVBS and DirecTV QPSK with SuperFEC™ for enhanced reception	Original	stv0910 16apsk 32apsk demodulator dvb-s2 vcm +6lfbga-168 dvb-s2 integrated receiver demodulator dvb-s2 dvb-s2 demodulator vcm dvb-s2 demodulator demodulator equalizer	PDF
STV0913 Abstract: LDPC decoder ip core DVB-S2 Tuner demodulator DVB-S2 integrated receiver demodulator dvb-s2 modem dvb-s receiver bit/DVB-S2 Tuner demodulator LDPC decoder LDPC decoder timing DVB st Contextual Info: STV0913 Multi-standard advanced demodulator for satellite digital TV broadcast set-top boxes Data brief Features • ■ ■ – – – – – Multi-standard demodulation – DVB-S2 QPSK and 8PSK – Legacy DVB-S and DirecTVTM QPSK – Multi-tap equalizer for RF reflection	Original	stv0913 10-bit 22-khz ldpc decoder ip core +8dvb-s2 tuner demodulator dvb-s2 integrated receiver demodulator dvb-s2 modem dvb-s receiver bit/dvb-s2 tuner demodulator ldpc decoder ldpc decoder timing dvb st	PDF
STB0899 Abstract: LNBP22 DVB-S2 demodulator DVB T transport stream processor DiSEqC DVB-S2 Tuner demodulator DVB-s demodulator demodulator Chip dvb-s2 DVB-s2 ldpc STB0899 datasheet Contextual Info: STB0899 Multistandard advance demodulator STB0899 Digital TV satellite set-top boxes DATA BRIEF DESCRIPTION The STB0899 advanced demodulator from STMicroelectronics enables digital set-top boxes to process base-band DVB-S2 signals into digital video transport stream data. This data is then	Original	stb0899 stb6100 lnbp22 dvb-s2 demodulator +7dvb t transport stream processor diseqc dvb-s2 tuner demodulator dvb-s demodulator demodulator chip dvb-s2 dvb-s2 ldpc stb0899 datasheet	PDF
STB0899 Abstract: LNBP22 DVB-S2 Tuner demodulator DVB-S2 demodulator Chip dvb-s2 DVB-s demodulator dvb-s2 tuner DVB-S2 demodulator ST stb0899 LDPC decoder Contextual Info: STB0899 Multistandard advance demodulator STB0899 Digital TV satellite set-top boxes DATA BRIEF DESCRIPTION The STB0899 advanced demodulator from STMicroelectronics enables digital set-top boxes to process base-band DVB-S2 signals into digital video transport stream data. This data is then	Original	stb0899 stb6100 lnbp22 dvb-s2 tuner demodulator +7dvb-s2 demodulator chip dvb-s2 dvb-s demodulator dvb-s2 tuner dvb-s2 demodulator st stb0899 ldpc decoder	PDF
bpsk modulation and demodulation using labview Abstract: fsk modulation and demodulation using labview MSK LabVIEW ask fsk psk vestigial sideband demodulation PSK modulation FSK labview MSK DSSS 64-PSK LDPC decoder timing Contextual Info: Tools for Digital and Analog Modulation/Demodulation Communications Analysis NI Modulation Toolkit for LabVIEW Bit Generation Visualization and Analysis • PRBS orders 5-31 • User-defined • Trellis diagrams • Constellation plot • 2D and 3D eye diagrams	Original	256-qam 16-fsk 64-psk 51551a-01 +102007-9256-101-d bpsk modulation and demodulation using labview fsk modulation and demodulation using labview msk labview ask fsk psk vestigial sideband demodulation psk modulation fsk labview msk dsss ldpc decoder timing	PDF
stv6110A Abstract: stx7109 STV0903B STV0903 ldpc decoder LQFP128-14 STV0903BAB STX7100 stx7100 jtag stv6110 Contextual Info: STV0903 Multi-standard advanced demodulator for satellite digital TV and data services set-top boxes Data Brief Features • ■ ■ DiSEqCTM 2.x interface GPIOs and interrupt lines Monitoring through I2C serial interface FSK modem – – – – Demodulation	Original	stv0903 lqfp-128-ep 14x14 stv6110a +8stx7109 stv0903b ldpc decoder lqfp128-14 stv0903bab stx7100 stx7100 jtag stv6110	PDF
qpsk AND 8PSK modulation VHDL CODE Abstract: XILINX vhdl code LDPC 16APSK LDPC encoder verilog vhdl code FOR 8PSK qpsk modulation VHDL CODE vhdl code for ldpc LDPC Decoder vhdl XC6SLX45-FGG484 dvb-s encoder design with fpga Contextual Info: LogiCORE IP DVB-S.2 FEC Encoder v2.0 DS505 December 2, 2009 Product Specification Introduction Overview The Xilinx DVB-S.2 FEC Encoder core provides designers with a Forward Error Correction FEC Encoding block for DVB-S.2 systems. The DVB-S.2 FEC Encoder core provides a complete	Original	ds505 qpsk and 8psk modulation vhdl code xilinx vhdl code ldpc 16apsk +7ldpc encoder verilog vhdl code for 8psk qpsk modulation vhdl code vhdl code for ldpc ldpc decoder vhdl xc6slx45-fgg484 dvb-s encoder design with fpga	PDF
10GBASE-T Abstract: RJ45 LAN port of motherboard CAT7 cables sgmii switch LDPC encoder APM96895 MACsec APM9689x 10gb RJ45 SMALL Contextual Info: Triveni Dual/Quad Port 10GBASE-T PHY PREL I M IN ARY PRO DU CT BRI EF The Triveni APM9689x family includes integrated dual and quad port PHYs supporting IEEE 802.3 10GBASE-T operation. Based on 40nm process technology and a state-of-the-art programmable DSP engine, the device is designed to	Original	10gbase-t apm9689x rj45 lan port of motherboard cat7 cables +6sgmii switch ldpc encoder apm96895 macsec 10gb rj45 small	PDF
lte turbo encoder Abstract: its 31567 data sheet xilinx lte TURBO decoder XTP025 LDPC encoder decoder ip core LDPC decoder ip core 24604 LTE DL Channel Encoder 25160 dvb-s encoder design with fpga Contextual Info: 30 IP Release Notes Guide XTP025 v1.6 June 24, 2009 Xilinx Intellectual Property (IP) cores including LogiCORE IP cores are delivered through software updates available from the Xilinx Download Center. The latest versions of IP products have been tested and are delivered with the current IP	Original	xtp025 l3/24/08 lte turbo encoder its 31567 data sheet +7xilinx lte turbo decoder ldpc encoder decoder ip core ldpc decoder ip core 24604 lte dl channel encoder 25160 dvb-s encoder design with fpga	PDF
LDPC decoder ip core Abstract: 33258 24604 lte turbo encoder LDPC decoder timing 3GPP LTE MIMO Decoder XTP025 223-28 LDPC encoder 1000BASE-X Contextual Info: 31 IP Release Notes Guide XTP025 v1.8 December 2, 2009 Xilinx Intellectual Property (IP) cores including LogiCORE IP cores are delivered through software updates available from the Xilinx Download Center. The latest versions of IP products have been tested and are delivered with the current IP	Original	xtp025 ldpc decoder ip core 33258 24604 +6lte turbo encoder ldpc decoder timing 3gpp lte mimo decoder 223-28 ldpc encoder 1000base-x	PDF
Contextual Info: ETL_dat-sw_en_5213-7748-22_V1600Cover.indd 1 Data Sheet \| 16.00 Broadcasting Test & Measurement R&S ETL TV Analyzer Specifications 02.09.2013 09:43:53 Version 16.00, September 2013 CONTENTS Definitions . 5	Original	v1600cover	PDF
STV0899 Abstract: STB6100 Single Chip dvb-s2 DVB-S2 demodulator stv0288 I2C STX7100 i2c tuner dvb-s2 i2c DVB-s2 ldpc dvb s2 nim Contextual Info: STNIM-SAT3 QPSK - 8PSK DVB-S2 NIM Target Specification Features Description • Multistandard QPSK and BPSK modulation ■ DVB-S up to 90 Mbps channel bit rate ■ Legacy DVB-S and DIRECTV ■ Loopthrough or single input on request ■ Input range 950 - 2150 MHz	Original	stv0899 stb6100 single chip dvb-s2 dvb-s2 demodulator +6stv0288 i2c stx7100 i2c tuner dvb-s2 i2c dvb-s2 ldpc dvb s2 nim	PDF
X557-AT2 Abstract: lp 8029 l4 Contextual Info: Intel X557-AT/AT2/AT4 10 GbE PHY Datasheet Networking Division ND Features:  10GBASE-T Performance — Ability to support worst case channels while reducing power and latency when channel characteristics permit:    Built-in thermal management capabilities — Enables deployment in thermally constrained	Original	x557-at/at2/at4 10gbase-t h7137nl g13-152t-038 +8g17-188t-038 g12-1jjt-038 jt4-1108hl rjtge1g4172j h130a-50 000-16-f-1010-tr-ns1 x557-at2 lp 8029 l4	PDF
vhdl code for ldpc decoder Abstract: G.975.1 XILINX vhdl code LDPC vhdl code for ldpc virtex 5 fpga utilization vhdl code for traffic light control XILINX vhdl code download LDPC vhdl code hamming LDPC encoder decoder ip core rs(255,239) FEC Contextual Info: Application Note: Virtex-4 and Virtex-5 Platform FPGA Families Forward Error Correction on ITU-G.709 Networks using Reed-Solomon Solutions R XAPP952 v1.0 December 5, 2007 Author: Michael Francis Summary The ITU-G.709, Interface for the Optical Transport Network (OTN) standard [Ref 1] describes	Original	xapp952 vhdl code for ldpc decoder g.975.1 xilinx vhdl code ldpc +7vhdl code for ldpc virtex 5 fpga utilization vhdl code for traffic light control xilinx vhdl code download ldpc vhdl code hamming ldpc encoder decoder ip core rs(255,239) fec	PDF

mx41 plc Abstract: 2-BIT Full-Adder CP20K NEC lcd inverter schematic NEC CP20K FPGA nec cmos CLS199 LDPC Decoder vhdl RAM64X4 9020 8pin Contextual Info: MAR i o 1983 C P20K 0 .8 -M IC R O N fp g a s NEC Electronics Inc. February 1993 Description Figure 1. CP20K FPGAs NEC Electronics Inc. and Crosspoint Solutions, Inc. have joined forces to offer to system designers an expedient way to prototype in Field Program m able Gate Arrays	OCR Scan	cp20k mx41 plc 2-bit full-adder nec lcd inverter schematic +6nec cp20k fpga nec cmos cls199 ldpc decoder vhdl ram64x4 9020 8pin	PDF
mip 291 Abstract: DIAGRAM pal 005a ic MIP 291 AM29116 X0953 29LS18 PAL16L8 LDPC encoder AM29xx PAL16R8 algorithm amd Contextual Info: a Am29116 A Microcoded Instruction Processor Based On The Am29116 Application Note Bv Robert e . Anderson ADVANCED MICRO DEVICES The MIP Board: A Microcoded 1-Code Processor Based on the Am29116 A. David Milton, Mitel Robert E. Anderson, AMD March, 1985. Table Of Contents	OCR Scan	am29116 ih-wcp-5m-12/85-0 7339a mip 291 +8diagram pal 005a ic mip 291 x0953 29ls18 pal16l8 ldpc encoder am29xx pal16r8 algorithm amd	PDF
full adder using Multiplexer IC 74151 Abstract: 74151 MUX 8-1 full subtractor using ic 74138 pin configuration IC 74151 Multiplexer IC 74151 modulo 16 johnson counter MUX 74157 MUX 74151 16 bit comparator using 74*85 IC binary to gray code conversion using ic 74157 Contextual Info: A dvance Inform ation, version 1.1 ’v'v' Crosspoint Solutions, Inc. C rosspoint has built the first field-program m able replacem ent for standard m ask-program m able gate arrays, the true F ield Program m able G ate A rray FPGA . System designers now have the flexibility and freedom to:	OCR Scan	full adder using multiplexer ic 74151 74151 mux 8-1 full subtractor using ic 74138 pin configuration ic 74151 +6multiplexer ic 74151 modulo 16 johnson counter mux 74157 mux 74151 16 bit comparator using 74*85 ic binary to gray code conversion using ic 74157	PDF
vhdl code for 8-bit BCD adder Contextual Info: A dvance Inform ation, version 1.1 ‘v ' v ' : Crosspoint Solutions, Inc. C rosspoint has built the first field-program m able replacem ent for standard m ask-program m able gate arrays, the true F ield P rogram m able G ate A rray FPGA . System designers now have the flexibility and freedom to:	OCR Scan	establis20 vhdl code for 8-bit bcd adder	PDF
HG62F Abstract: V/HG62F HG62F43 Contextual Info: #U 210 HG62F SERIES Hitachi CMOS Gate Array High I/O to Gate Ratio JANUARY, 1990 0 H IT A C H I The F series consists of 6 masterslices ranging from 2,178 to 10,076 available gates with high I/O pin counts ranging from 136 pins to 208 pins. The HG62F series is a mastersliced gate array fabricated on 1.0	OCR Scan	hg62f v/hg62f hg62f43	PDF
LD124 Abstract: Z89321 CS4215 CS4216 PCM 1756 Contextual Info: USING THE Z89321/371/391 CODEC INTERFACE APPLICATION N OTE ApplicationNote USINGTHEZ89321/371/391CODECINTERFACE With 20 MIPProcessing Power and a Harvard Bus Structure, the Z89321/371/391 Provides Efficient Execution of Compression, Filtering, Speech Coding, Frequency Detection, and other Routines Vital to	Original	z89321/371/391 usingthez89321/371/391codecinterface 16-bit z89321 +5ap96dsp1100 ld124 cs4215 cs4216 pcm 1756	PDF
G13-152T-038 Abstract: ntp 3200 ic digital amplifier PEC 4179 DIODE LP 8029 l2 Honeywell DBM 01 PCB Intel 82437 Intel 82456 DTM 65512 1G 26SD 7A50020001 Contextual Info: Intel Ethernet Controller X540 Datasheet PRODUCT FEATURES General  Serial flash interface  Configurable LED operation for software or OEM customization of LED displays  Device disable capability  Package size - 25 mm x 25 mm Networking  10 GbE/1 GbE/100 Mb/s copper PHYs integrated on-chip	Original	gbe/100 g13-152t-038 ntp 3200 ic digital amplifier pec 4179 diode +7lp 8029 l2 honeywell dbm 01 pcb intel 82437 intel 82456 dtm 65512 1g 26sd 7a50020001	PDF
manual SPARTAN-3 XC3S400 evaluation kit Abstract: hcl l21 usb power supply circuit diagram verilog code for Modified Booth algorithm vhdl code for lcd of spartan3E UG331 TT 2222 Horizontal Output Transistor pins out dia verilog for 8 point fft using FPGA spartan3 vhdl code for ldpc decoder types of multipliers ge fanuc cpu 331 Contextual Info: Spartan-3 Generation FPGA User Guide Extended Spartan-3A, Spartan-3E, and Spartan-3 FPGA Families UG331 v1.7 August 19, 2010 R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development	Original	ug331 guides/ug332 manual spartan-3 xc3s400 evaluation kit hcl l21 usb power supply circuit diagram +7verilog code for modified booth algorithm vhdl code for lcd of spartan3e tt 2222 horizontal output transistor pins out dia verilog for 8 point fft using fpga spartan3 vhdl code for ldpc decoder types of multipliers ge fanuc cpu 331	PDF
vhdl code for lcd of spartan3E Abstract: verilog code for Modified Booth algorithm vhdl code for rs232 receiver ge fanuc cpu 331 ug331 vhdl ethernet spartan 3a spartan 3e vga ucf barco 16 BIT ALU design with verilog/vhdl code TUTORIALS xilinx FFT Contextual Info: Spartan-3 Generation FPGA User Guide Extended Spartan-3A, Spartan-3E, and Spartan-3 FPGA Families UG331 v1.5 January 21, 2009 R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development	Original	ug331 guides/ug332 vhdl code for lcd of spartan3e verilog code for modified booth algorithm +7vhdl code for rs232 receiver ge fanuc cpu 331 vhdl ethernet spartan 3a spartan 3e vga ucf barco 16 bit alu design with verilog/vhdl code tutorials xilinx fft	PDF
UG331 Abstract: CWda04 XAPP256 manual SPARTAN-3 XC3S400 evaluation kit vhdl code for rs232 receiver hcl l21 usb power supply circuit diagram hcl p38 CIRCUIT diagram R80515 XC3SD1800A-FG676 vhdl ethernet spartan 3a Contextual Info: Spartan-3 Generation FPGA User Guide Extended Spartan-3A, Spartan-3E, and Spartan-3 FPGA Families UG331 v1.6 December 3, 2009 R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development	Original	ug331 guides/ug332 cwda04 xapp256 +7manual spartan-3 xc3s400 evaluation kit vhdl code for rs232 receiver hcl l21 usb power supply circuit diagram hcl p38 circuit diagram r80515 xc3sd1800a-fg676 vhdl ethernet spartan 3a	PDF

LDPC DECODER TIMING Search Results

LDPC DECODER TIMING Result Highlights (5)

LDPC DECODER TIMING Datasheets Context Search

STV0910

STV0913

STB0899

STB0899

bpsk modulation and demodulation using labview

stv6110A

qpsk AND 8PSK modulation VHDL CODE

10GBASE-T

lte turbo encoder

LDPC decoder ip core

STV0899

X557-AT2

vhdl code for ldpc decoder

mx41 plc

mip 291

full adder using Multiplexer IC 74151

vhdl code for 8-bit BCD adder

HG62F

LD124

G13-152T-038

manual SPARTAN-3 XC3S400 evaluation kit

vhdl code for lcd of spartan3E

UG331