LD3A Search Results

csc 9803

Abstract: QML-38534 LA4-DA BMS SYSTEM qualification CE7Y
Contextual Info: REVISIONS LTR A DESCRIPTION DATE YR-MO-DA Add device type REV APPROVED 98-12-10_ K. A. Cottonqim A A A A A A A A A A A A A A A A A A A 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 REV A

AD14060

Abstract: ad14060lbf AD14060L ADSP-21060 lA1d ms2107 ADSP-20160 22760a
Contextual Info: Quad-SHARC DSP Multiprocessor Family AD14060/AD14060L CS TIMEXP LINK 1 LINK 3 LINK 4 IRQ2–0 FLAG2, 0 CPA SPORT 1 SPORT 0 TCK, TMS, TRST FLAG1 FLAG3 TDO LINK 0 LINK 2 LINK 5 TDI SHARC_B EBOOT, LBOOT, BMS EMU CLKIN RESET SPORT 0 TCK, TMS, TRST FLAG1 FLAG3

LC2D

Abstract: SMD transistor n36 368C smd at6 TFSC0 AD14060 AD14160 AD14160L ADSP-21060 socket am3 mounting
Contextual Info: a AD14160/ AD14160L GENERAL DESCRIPTION The AD14160/AD14160L Quad-SHARC Ceramic Ball Grid Array CBGA puts the power of the first generation AD14060 (CQFP) DSP multiprocessor into a very high density ball grid array package; now with additional link and serial I/O pinned

csc 9803

Abstract: brx 149 QML-38534 2DT8 dty1 inspection sampling plan BMS qualification 237dt
Contextual Info: REVISIONS LTR DESCRIPTION DATE YR-MO-DA APPROVED A Corrections to table I. 98-03-23 K. A. Cottongim B Add device type 02. 99-10-08 Ray Monnin C Editorial corrections to tables I, III, and figures 1, 2, 3, 4. Update drawing boilerplate. 03-03-31 Raymond Monnin

hbr Y1

Abstract: lc1d
Contextual Info: BACK a AD14160/ AD14160L GENERAL DESCRIPTION The AD14160/AD14160L Quad-SHARC Ceramic Ball Grid Array CBGA puts the power of the first generation AD14060 (CQFP) DSP multiprocessor into a very high density ball grid array package; now with additional link and serial I/O pinned

g31 m7 te

Abstract: LC2-D LA4-DA adsp20 Socket AM2 AL-20 bmsa
Contextual Info: a Quad-SHARC DSP Multiprocessor Family AD14160/AD14160L OLE AD14160/ AD14160L GENERAL DESCRIPTION The AD14160/AD14160L Quad-SHARC Ceramic Ball Grid Array CBGA puts the power of the first generation AD14060 (CQFP) DSP multiprocessor into a very high density ball grid

LSK 331

Abstract: QML-38534
Contextual Info: REVISIONS LTR DESCRIPTION DATE APPROVED YR-MO-DA A_ Corrections to table 98-03-23_ K. A. Cottonqim B_ Add device type Rav Monnin

headland 386

Abstract: transistor zo 607 MA 7S b2211 full subtractor using ic 74138
Contextual Info: LOGIC LCB300K Cell-Based 5 Volt ASIC Products Databook October 1994 This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of LSI Logic Corporation.

g31 m7 te

Abstract: wiring diagram uni 45 ta
Contextual Info: Quad-SHARC DSP Multiprocessor Family ANALOG DEVICES AD 14160/AD 14160L FUNCTIONAL BLOCK DIAGRAM o LINK 4 £ CPA F S P O R TI SPORTO TDI im Itllllll o C S i i i i |o a * □ □ □ □ |s= 3 3 3 £ LL3 LINK 0 ID « , ^ SHARC_A I— CO oc I- LINKS TDO CPA

SB-TSI

Abstract: ic sj 2038 reset QML-38534 ir020
Contextual Info: REVISIONS LTR DESCRIPTION APPROVED DATE YR-MO-DA REV SHEET 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 9 10 11 12 13 14 REV SHEET REV STATUS OF SHEETS REV SHEET PMIC N/A STANDARD M ICRO CIRCUIT

Contextual Info: Quad-SHARC DSP Multiprocessor Family AD14060/AD14060L ANALOG DEVICES PERFORMANCE FEATU RES ADSP-21060 Core Processor . . . x4 480 MFLOPS Peak, 320 MFLOPS Sustained 25 ns Instruction Rate, Single-Cycle Instruction Execution-Each of Four Processors 16 Mbit Shared SRAM (Internal to SHARCs)

Contextual Info: Quad-SHARC * DSP Multiprocessor Family AD14060 ANALOG DEVICES PERFORMANCE FEATURES ADSP-21060 Core Processor . . x4 480 MFLOPS Peak, 320 MFLOPS Sustained 25 ns Instruction Rate, Single-Cycle Instruction Execution-Each of Four Processors 16 M b it Shared SRAM (Internal to SHARC™s)

ADSP-20160

Abstract: AD14060 SHARC SHARC 21060 AD14060L ADSP-21060 ADSP-21060 reference manual for registers initial
Contextual Info: a GENERAL DESCRIPTION The AD14060/AD14060L Quad-SHARC is the first in a family of high performance DSP multiprocessor modules. The core of the multiprocessor is the ADSP-21060 DSP microcomputer. The AD14060/AD14060L modules have the highest performance —density and lowest cost—performance ratios of any in

ADSP-20160

Abstract: ADSP-14060 LA3C BittWare ID101 AD14060
Contextual Info: BACK a GENERAL DESCRIPTION The AD14060/AD14060L Quad-SHARC is the first in a family of high performance DSP multiprocessor modules. The core of the multiprocessor is the ADSP-21060 DSP microcomputer. The AD14060/AD14060L modules have the highest performance —density and lowest cost—performance ratios of any in

csc 9803

Abstract: QML-38534 203DT 55DT
Contextual Info: REVISIONS LTR A DESCRIPTION DATE YR-MO-DA APPROVED 98-12-10 K. A. Cottongim Add device type 02. REV A A A A A A A A A A A A A A A A A A A SHEET 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 REV A A A A A A A A A A A A A A A A A A A A SHEET 15

Contextual Info: Quad-SHARC DSP Multiprocessor Family AD14060/AD14060L PERFORMANCE FEATURES CS TIMEXP LINK 1 LINK 3 LINK 4 IRQ2–0 FLAG2, 0 CPA SPORT 1 SPORT 0 TCK, TMS, TRST FLAG1 FLAG3 TDO LINK 0 LINK 2 LINK 5 TDI SHARC_B EBOOT, LBOOT, BMS EMU CLKIN RESET SPORT 0 TCK, TMS, TRST

DP820

Abstract: TD647
Contextual Info: DP8420A/DP8421A/DP8422A S3 National Æ M S e m ic o n d u c to r DP8420A/21A /22A microCMOS Programmable 256k/1M /4M Dynamic RAM Controller/Drivers General Description Features The DP8420A/21A/22A dynamic RAM controllers provide a low cost, single chip interface between dynamic RAM and