LC-2-G DRAWING Search Results

Contextual Info: HITACHI KAOHSIUNG HITACHI ELECTRONICS CO.,LTD P.O. BOX 26-27 2,13TH EAST ST. K.E.P.Z. KAOHSIUNG TAIWAN R.O.C. TEL: 07 8215811 (7 LINE) FAX:(07) 8215815 FOR MESSRS : DATE: May. 13.2008 CUSTOMER’S ACCEPTANCE SPECIFICATIONS SP14N01L6VLCA CONTENTS No. ITEM

Contextual Info: TPA3101D2 HTQFP QFN www.ti.com SLOS473 – DECEMBER 2005 10-W STEREO CLASS-D AUDIO POWER AMPLIFIER FEATURES APPLICATIONS • • • • • • • • • • • 10-W/ch into an 8-Ω Load From a 13-V Supply 9.2-W/ch into an 8-Ω Load From a 12-V Supply

piezoelectric control circuit diagram

Contextual Info: UCC2975, UCC2976, UCC2977 UCC3975, UCC3976, UCC3977 SLUS499A – NOVEMBER 2001 – REVISED JANUARY 2002 MULTIĆTOPOLOGY PIEZOELECTRIC TRANSFORMER CONTROLLER FEATURES D 3-V to 13.5-V Operation D Supports Flyback UCC3975 , Half-Bridge D D D D D DESCRIPTION

gsr 600

Abstract: SLUA3 variable ramp generator
Contextual Info: TPS40060 TPS40061 8 www.ti.com SLUS543D – DECEMBER 2002 – REVISED SEPTEMBER 2004 WIDE-INPUT SYNCHRONOUS BUCK CONTROLLER FEATURES • • • • • • • • • • • DESCRIPTION Operating Input Voltage 10 V to 55 V Input Voltage Feed-Forward Compensation

Contextual Info: 6,4 mm y 5,0 mm TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 4.5-V TO 20-V INPUT, 6-A OUTPUT SYNCHRONOUS PWM SWITCHER WITH INTEGRATED FET SWIFT FEATURES • • • • • • • • • • • DESCRIPTION 40 mΩ MOSFET Switch for High Efficiency at

Contextual Info: pS mm Aperture Package Schematic Emitter Sensor DUAL CHANNEL SLOTTED T111N 1T Ll 'DI VDKTLT1 PITLi 'P K aC VW Ti lTl fvTlTl H21A3 Typ. T‘ o f f H21A2 Typ. W Ton <Tf * Ip = 5mA Ip = 20mA Ip = 30mA v cc = 5V, \ K)R= Ip = 1mA Ip = 30mA Ip = 1mA Ip = 30mA 60

Contextual Info: 6,4 mm y 5,0 mm TPS54350 www.ti.com SLVS456C − OCTOBER 2003 − REVISED OCTOBER 2004 4.5ĆV TO 20ĆV INPUT, 3ĆA OUTPUT SYNCHRONOUS PWM SWITCHER WITH INTEGRATED FET SWIFT FEATURES D 100 mΩ, 4.5-A Peak MOSFET Switch for High D D D D D D D D D Efficiency at 3-A Continuous Output Current

TAS5100

Contextual Info: TAS5100 SLLS419B – MARCH 2001 – REVISED NOVEMBER 2001 TRUE DIGITAL AUDIO AMPLIFIER TAS5100 PWM POWER OUTPUT STAGE D Internet Music Appliance D Mini/Micro Component Systems FEATURES D TAS5000 + TAS5100 TDAA System-High D D D D D D D D Quality Digital Audio Amplification

Contextual Info: TAS5152 www.ti.com SLES127A − FEBRUARY 2005 − REVISED NOVEMBER 2005 TM STEREO DIGITAL AMPLIFIER POWER STAGE FEATURES D 2x125 W at 10% THD+N Into 4-W BTL D 2×98 W at 10% THD+N Into 6-W BTL D 2×76 W at 10% THD+N Into 8-W BTL D 4×45 W at 10% THD+N Into 3-W SE

Contextual Info: IDT7210L 16 x 1 6 PARALLEL CMOS MULTIPLIER-ACCUMULATOR Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • 16 x 16 parallel m ultiplier-accumulator with selectable • • accumulation and subtraction High-speed: 20ns m ultiply-accumulate time ID T 7 2 1 0 features selectable accum ulation, subtraction,

TLC5904

Contextual Info: TLC5904 LED DRIVER SLLS391 – NOVEMBER 1999 D D D D D D D Drive Capability and Output Counts – 80 mA Current Sink x 16 Bits – 120 mA (Current Sink) x 8 Bits Constant Current Output Range – 5 to 80 mA/10 to 120mA (Selectable by MODE Terminal) (Current Value Setting for

FAIU

Contextual Info: p f t iO M O D O M v in te i 80C186 CHMOS HIGH INTEGRATION 16-BIT MICROPROCESSOR Operation Modes Include: — Enhanced Mode Which Has — DRAM Refresh Control Unit — Power-Save Mode — Direct Interface to New Numerics Coprocessor — Compatible Mode — NMOS 80186 Pin-for-Pin

Contextual Info: IB M 1 1 M 2 7 3 5 H 2M x 72 DRAM MODULE Features • 168 Pin JEDEC Standard, 8 Byte Dual In-line Memory Module Optimized for ECC applications System Performance Benefits: • 2Mx72 Fast Page Mode DIMM - Buffered inputs except RAS, Data - Reduced noise (32 Vss/Vcc Pir|s)

Contextual Info: IDT70825S/L HIGH SPEED 128K 8K X 16 BIT SEQUENTIAL ACCESS RANDOM ACCESS MEMORY (SARAM ) F e a tu re s ♦ ♦ ♦ ♦ * High-speed access * - Military: 35/45ns (max.) - Commercial: 20/25/35/45ns (max.) Low-power operation - IDT70825S - Address based flags for buffer control

Contextual Info: = =— ~ s z ~ - -Z _=-Z T IB M 1 1 T 1 6 4 0 L P 1M x 64 144 PIN SO DIMM Features • 144 Pin JEDEC Standard, 8 Byte Small Outline Dual In-line Memory Module with 8 Byte busses • Au contacts • Optimized for byte-write non-parity applications • Performance:

LM2575

Abstract: LM257 jedec package TO-220 lm2575 adj
Contextual Info: LM2575 1ĆA SIMPLE STEPĆDOWN SWITCHING VOLTAGE REGULATOR SLVS569B − JANUARY 2005 − REVISED APRIL 2005 D Fixed 3.3-V, 5-V, 12-V, and 15-V Options D D D D GND ON/OFF FEEDBACK GND OUTPUT VIN KV TO-220 STAGGERED LEADS PACKAGE (TOP VIEW) (SIDE VIEW) 5 4

LCD Gamma Buffers

Abstract: LCD gamma buffer low power mode
Contextual Info: BUF12800 SBOS315A − DECEMBER 2004 − REVISED JULY 2005 REFERENCE VOLTAGE GENERATOR for LCD GAMMA CORRECTION FEATURES D D D D D D D D D D D APPLICATIONS 12-CHANNEL GAMMA CORRECTION 10-BIT RESOLUTION DOUBLE-BUFFERED DAC REGISTERS INTEGRATED REFERENCE BUFFERS

Contextual Info: The IDT7203/7204/7205/7206 are dual-port memory buff­ ers with internal pointers that load and empty data on a firstin/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow and expansion logic to allow for unlimited expansion capability in both word size and

SI3016

Contextual Info: TMS320C54V90 EMBEDDED V.90 MODEM DSP SPRS165F − JULY 2001 − REVISED OCTOBER 2003 D Provides Two-Chip Modem Solution D Data Rates from 300 bps to 56 Kbps D Data Modulation Standards D V.90, V.34, V.32bis, V.32, V.22bis, V.22, V.23, V.21 and V.23 Reversible Minitel , Bell 212,

Contextual Info: SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR SGUS020B – JUNE 1996 – REVISED SEPTEMBER 2001 D Military Operating Temperature Range: D D D D D D D D D D D D D D D D D ÉÉ ÉÉ 100 132 ÉÉ ÉÉ 1 99 33 67 ÉÉ ÉÉ 66 D ÉÉ ÉÉ ÉÉ ÉÉ 34 D D – 55°C to 125°C

Contextual Info: TSB41BA3AĆEP IEEE 1394b THREEĆPORT CABLE TRANSCEIVER/ARBITER SGLS253A—OCTOBER 2004—REVISED JULY 2005 D Controlled Baseline D D D D D D D D D D D D Low-Power Automotive Sleep Mode − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of

Contextual Info: TAS5112A www.ti.com SLES094A - OCTOBER 2003 - REVISED MARCH 2004 TM DIGITAL AMPLIFIER POWER STAGE FEATURES D 50 W per Channel BTL Into 6 Ω (Stereo) D 95-dB Dynamic Range With TAS5026 D Less Than 0.1% THD+N (1 W RMS Into 6 Ω) D Less Than 0.2% THD+N (50 W RMS into 6 Ω)

Intel overdrive

Contextual Info: in t e i Intel486 SX M ICROPROCESSOR IM PORTANT— Read This Section Before Reading The Rest Of The Data Sheet This data sheet describes the Intel486 SX microprocessor, the Intel OverDrive™ Processor, and the l n t e l 4 8 7 TM S X Math Coprocessor. All normal text describes the functionality for the Intel486 SX microproces­

XC90

Abstract: intel 82358
Contextual Info: 82355 BUS MASTER INTERFACE CONTROLLER BMIC • Designed for use in 32-Bit EISA Bus Master Expansion Board Designs — Integrates Three interfaces (EISA, Local CPU, and Transfer Buffer) ■ Supports 16- and 32-Bit Burst Transfers — 33 Mbytes/Sec Maximum Data