L20RA Search Results

Contextual Info: PA L20RA1O ^<y- - 203- Series 24 33 . Input 01Feedback ^1 n a max A STD A2 A4 B B2 C fuse on max 30 ns fuse off max 35 ns max 30 ns max 20 ns Z tpd enable X Input clock th 20 ns 30 ns output max 30 ns fuse on min 10 ns fu se off min min 20 ns min 20 ns min

Contextual Info: Lattice •■■■■ ■■■■■ FEATURES ■HIGH PERFORMANCE E’CMOS TECHNOLOGY — 10 ns Maximum Propagation Delay — Fmax =71.4 MHz — 11 ns Maximum from Clock Input to Data Output — TTL Compatible 8 mA Outputs — UltraMOS® Advanced CMOS Technology

Contextual Info: Lattice L20RA10 High-Speed Asynchronous E2CMOS PLD Generic Array Logic ; Semiconductor I Corporation FUNCTIONAL BLOCK DIAGRAM FEATURES • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 7.5 ns Maximum Propagation Delay — Fmax = 83.3 MHz — 9 ns Maximum from Clock Input to Data Output

Contextual Info: Lattice G A L 2 0 R A 1 0 / 8 8 3 High-Speed Asynchronous E*CMOS PLD Generic Array Logic F U N C T IO N A L B L O C K D IAG RAM FE A TU R E S • HIGH PERFORMANCE E*CM O S* TECHNOLOGY — 20 ns Maximum Propagation Delay — Fmax = 41.7 MHz — 20 ns Maximum from Clock Input to Data Output