J681 Search Results

sangamo

Abstract: 016C P711U E152U Sangamo 500 350G P422U Sangamo 066
Contextual Info: RADIAL LEADED CAPACITORS Ultra-Low Impedance High Frequency Grade, 105°C Type 350 Standard ♦+♦ COE SANGAMO+ 01 *0 - 3 2 ! With a solid aluminum top type 350 is the lowest inductance radial leaded type available. Its 4 to 6nH typical ESL provides self resonant frequencies usually

Contextual Info: HIGH-SPEED 8K x 9 DUAL-PORT IDT7015S/L STATIC RAM I n t e g r a t e d D e v iz e T e c h n o lo g y , l i e . FEATURES: • True Dual-Ported m em ory cells which allow sim ulta­ neous reads of the sam e m em ory location • H igh-speed access — M ilitary: 20/25/35ns max.

Contextual Info: HIGH-SPEED 36K 4K x 9-BIT SYNCHRONOUS DUAL-PORT RAM PRELIMINARY IDT70914S Integ ra te d D evice Technology, Inc. FEATURES: DESCRIPTION: • High-speed clock-to-data output times — Military: 20/25ns (max.) — Commercial: 15/20/25ns (max.) • Low-power operation

Contextual Info: dt | ; HIGH-SPEED 16Kx 8 DUAL-PORT STATIC RAM IDT7006S/L In te g ra te d De v ic e T e ch n o lo g y, Inc. FEATURES: • • • True Dual-Ported m em ory cells w hich allow sim ulta­ neous access of the sam e m em ory location • H igh-speed access — M ilitary: 20/25/35/55/70ns max.)

Contextual Info: HIGH-SPEED 16Kx 8 DUAL-PORT STATIC RAM IDT7006S/L Integrated Device Technology, Inc. M/S = L for BUSY input on Slave • Interrupt Flag • On-chip port arbitration logic • Full on-chip hardware support of semaphore signaling between ports • Fully asynchronous operation from either port

Contextual Info: |9 | N a HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM w Éy IDT7005S/L Integrated Device Technology, Inc. • Interrupt Flag • On-chlp port arbitration logic • Full on-chip hardware support of semaphore signaling between ports • Fully asynchronous operation from either port

Contextual Info: HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM ydt IDT7015S/L Integrated De^/ice Technology, Inc. FEATURES: • True Dual-Ported m em ory cells w hich allow sim ulta­ neous access of the sam e m em ory location • H igh-speed access — M ilitary: 20/25/35ns max.)

Contextual Info: bbE D INTEGRATE» DEVICE B 4ÔSS771 0015534 bMT « I D T CMOS SyncFlFO 256 X 18, 512 X 18,1024 x 18, 2048 x 18 and 4 096x18 ID T 7 2 2 0 5 L B ID T 7 2 2 1 5 L B ID T 7 2 2 2 5 L B ID T 7 2 2 3 5 L B ID T 7 2 2 4 5 L B Integrated Device Technology, Inc.

Contextual Info: HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM IDT7015S/L FEATURES: * * True Dual-Ported memory cells which allow simultaneous reads of the sam e memory location * * * B u sy and Interrupt Flag - Military:20/25/35ns max. * On-chip port arbitration logic - Commercial: 12/15/17120125135ns (max.)

Contextual Info: HIGH-SPEED 4K x 9 SYNCHRONOUS DUAL-PORT STATIC RAM PRELIMINARY IDT70914S In tegrated D e v ic e T e c h n o lo g y , Inc. FEATURES: DESCRIPTION: • H igh-speed clock-to-data output tim es — Military: 20/25ns max. — C om m ercial: 15/20/25ns (max.) • Low -power operation

Contextual Info: HIGH-SPEED 8K x 9 DUAL-PORT M J IDT7015S/L STATIC RAM Integrated Device Technology, Inc. FEATURES: • True Dual-Ported memory cells which allow simulta­ neous reads of the same memory location • High-speed access — Military: 20/25/35ns max. — Commercial: 12/15/17/20/25/35ns (max.)

Contextual Info: IDT7133SA/LA IDT7143SA/LA CMOS DUAL-PORT RAMS 3 2 K 2 K x 16-BIT Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • High-speed access — Military: 35/45/55/70/90ns (max.) — Com mercial: 25/35/45/55/70/90ns (max.) • Low-power operation — IDT7133/43SA

Contextual Info: IDT7133SA/LA IDT7143SA/LA HIGH SPEED 2 K X 16 DUAL-PORT SRAM F e a tu re s ♦ High-speed access ♦ BUSY output flag on IDT7133; BUSY input on IDT7143 - M ilitary: 25/35/45/55/70/90ns max. ♦ Fully asynchronous operation from either port - Industrial: 55ns (max.)

Contextual Info: 16-BIT TRI-PORT BUS EXCHANGER IDT73720/A Integrated D evice T echnology, Inc. FEATURES: DESCRIPTION: • High-speed 16-bit bus exchange for interbus communica­ tion in the following environments: — Multi-way interleaving memory — Multiplexed address and data busses

Contextual Info: HIGH-SPEED 1 6 K X 9 DUAL-PORT STATIC RAM ID T 7 0 1 6 S /L Features using the Master/Slave select when cascading more than * True Dual-Ported memory cells which allow sim ultaneous one d e v i c e _ reads of the sam e memory location M/S = V ih for B U S Y output flag on Master

Contextual Info: HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM IDT7005S/L In te g ra te d D e v ic e T ec h nology, In c . FEATURES: • Interrupt Flag • On-chip port arbitration logic • Full on-chip hardware support of semaphore signaling between ports • Fully asynchronous operation from either port

J681

Abstract: 2SJ681 tr j681
Contextual Info: J681 東芝電界効果トランジスタ シリコンPチャネルMOS形 U-MOSIII J681 ○ リレー駆動DC−DC コンバータ用 ○ モータドライブ用 １．５±０．２ 単位: mm ６．５±０．２ ５．２±０．２ ０．６ MAX．

A12L

Abstract: IDT7005 IDT7005L IDT7005S
Contextual Info: IDT7005S/L HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM Features ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access – Military: 20/25/35/55/70ns max. – Industrial: 35/55ns (max.) – Commercial:15/17/20/25/35/55ns (max.)

2746 transistor

Abstract: IDT7133 IDT7143 J68 10A K 2746
Contextual Info: IDT7133SA/LA IDT7143SA/LA HIGH SPEED 2K X 16 DUAL-PORT SRAM Features ◆ ◆ ◆ ◆ ◆ ◆ High-speed access – Military: 25/35/45/55/70/90ns max. – Industrial: 25/35/55ns (max.) – Commercial: 20/25/35/45/55/70/90ns (max.) Low-power operation – IDT7133/43SA

02-Dl

Abstract: 72235 PGA 56C315 43536
Contextual Info: CMOS SyncFIFO 256 x 18, 512 x 18,1024 x 18, 2048 x 18 and 4096 x 18 FEATURES: • • • • • • • • • • • • • • • • • 256 x 18-bit organization array 72205LB 512 x 18-bit organization array (72215LB) 1024 x 18-bit organization array (72225LB)

16kx8 static ram ttl

Abstract: 2640I 08ND
Contextual Info: jg r -f HIGH-SPEED 32Kx 8 DUAL-PORT STATIC RAM PRELIMINARY IDT7007S/L In te g ra te d D evice T echnology, Inc. FEATURES: • IDT7007 easily expands data bus width to 16 bits or more using the Master/Slave select when cascading more than one device • M/S= H for BUSY output flag on Master

Contextual Info: PARALLEL BIDIRECTIONAL FIFO 512 x 18 & 1,024x18 IDT72511 IDT72521 îite g z a te d D ev ice T ech n ology, l i e . FEATURES: • Two side-by-side FIFO m em ory arrays for bidirectional data transfers • 5 1 2 x 1 8-B it - 512 x 18-Bit ID T72511 • 1,024 x 18-Bit - 1,024 x 18-Bit (IDT72521)

C5857

Abstract: C5352 L7970
Contextual Info: INTEGRATE» DEVICE bflE j m 4fl2S771 Q Q x 4g23 ^ Tb mil>T HIGH-SPEED 36K 4K x 9-BIT SYNCHRONOUS DUAL-PORT RAM IDT7099S Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • High-speed clock-to-data output tim es — Military: 20/25/30ns (max.) — C om m ercial: 15/20/25ns (max.)

1250-SS

Contextual Info: HIG H -S P E E D 8K x 8 D U A L - P O R T STATIC RAM FEATURES: • • • • • True D ual-Ported m em ory cells which allow sim ulta­ neous reads ot the sam e m em ory location High-speed access — M ilitary: 20/25/35/55/70ns max. — Industrial: 35/55ns (max.)