J1993 Search Results

Contextual Info: |U |I C R O N 128K X M T 58C 1289 9 S Y N C H R O N O U S SRAM 128K x 9 SRAM SYNCHRONOUS SRAM FULLY REGISTERED INPUTS AND OUTPUTS FEATURES PIN ASSIGNMENT Top View T im ing specific to SPARC m icroprocessor Fast cycle times: 12,16.6 and 20ns Fast clock to d ata valid: 6, 8 and 10ns

RRH cl2

Abstract: BBU RRH
Contextual Info: MT4C4001 J L 1 MEG X 4 DRAM I^IICRDN DRAM 1 MEG x 4 DRAM DRAM STANDARD OR LOW POWER, EXTENDED REFRESH FEATURES • 1,024-cycle refresh distributed across 16ms (MT4C4001J) or 128ms (MT4C4001J L) • Industry-standard x4 pinout, timing, functions and packages

D1-D16

Contextual Info: PRELIMINARY M T56C 16K 16B 2 16K X 16 L A T C H E D S R A M |U |IC = R O N LATCHED SRAM 16K X 16 SRAM WITH ADDRESS/ DATA INPUT LATCHES, BYTE ENABLES FEATURES • • • • • • • OPTIONS 52-Pin PLCC SC-2 52-Pin PQFP (SC-5) S e m iti 8 < <!olcûlcü > >15 < IO < < o

Contextual Info: I ADVANCE M T4 L C 2M 8B 1/2 S IEG X 8 W IDE DRAM MICRON WIDE DRAM 2 MEG X 8 DRAM 5.0V SELF REFRESH (MT4C2M8B1/2 S) 3.0/3.3V, SELF REFRESH (MT4LC2M8B1/2 S) FEATURES PIN ASSIGNMENT (Top View) OPTIONS 28 ] Vss 27 ] 0 Q 8 26 ] DQ7 Vcc [ 1 001 C 2 OQ2 [ 3 DQ3 [ 4

MT42C8254

Contextual Info: MT42C8254 256K X 8 VRAM M IC R O N VRAM 256K X 8 DRAM WITH 512x8 SAM FEATURES • Industry-standard pinout, tim ing and functions • NIBBLE 4-bit W RITE and M ASKED W RITE access cycles • High-perform ance, CM O S silicon-gate process • Single +5V ±10% pow er supply