IPUG21 Search Results

ddr phy

Abstract: master ATM controller ddr phy design
Contextual Info: ispLever CORE TM UTOPIA Level 3 PHY Receive Interface User’s Guide October 2003 ipug21_01 Lattice Semiconductor UTOPIA Level 3 PHY Receive Interface Introduction The UTOPIA Level 3 PHY Receive core, UTOP3-PHYR, is one of four UTOPIA Level 3 cores available from Lattice.