IO18RSB1 Search Results

QN68

Abstract: VQ100 actel part markings
Contextual Info: Advance v0.4 ProASIC®3 nano Flash FPGAs Features and Benefits Advanced I/Os Wide Range of Features • 10 k to 250 k System Gates • Up to 36 kbits of True Dual-Port SRAM • Up to 71 User I/Os Reprogrammable Flash Technology • • • • 130-nm, 7-Layer Metal 6 Copper , Flash-Based CMOS Process

actel vqfp

Abstract: IO87RSB1
Contextual Info: ProASIC3 nano Packaging 3 – Package Pin Assignments 48-Pin QFN Pin 1 48 1 Notes: 1. This is the bottom view of the package. 2. The die attach paddle of the package is tied to ground GND . Note For Package Manufacturing and Environmental information, visit the Resource Center at

IO91RSB2

Abstract: Datasheet AGLN060 81-Pin Datasheet AGLN020 AGLN020 IO10RSB0 AGLN010
Contextual Info: IGLOO nano Packaging 3 – Package Pin Assignments 36-Pin UC Pin 1 Pad Corner 6 5 4 3 2 1 A B C D E F Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at .

QN68

Abstract: VQ100 PAC11 ProASIC3 handbook
Contextual Info: Advance v0.5 ProASIC®3 nano Flash FPGAs Features and Benefits Advanced I/Os Wide Range of Features • 10 k to 250 k System Gates • Up to 36 kbits of True Dual-Port SRAM • Up to 71 User I/Os Reprogrammable Flash Technology • • • • 130-nm, 7-Layer Metal 6 Copper , Flash-Based CMOS Process

Contextual Info: IGLOO nano Handbook IGLOO nano Handbook Table of Contents Low-Power Flash Device Handbooks Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i Section I – IGLOO nano Datasheet IGLOO nano Low-Power Flash FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Actel igloo

Abstract: Datasheet AGLN020 CS81 VQ100 RAM51 AGLN010
Contextual Info: Advance v0.8 IGLOO nano Low-Power Flash FPGAs with Flash*Freeze Technology Features and Benefits High-Performance Routing Hierarchy Low Power Advanced I/Os • Segmented, Hierarchical Routing and Clock Structure • • • • • nanoPower Consumption—Industry’s Lowest Power

Contextual Info: Revision 9 ProASIC3 nano Flash FPGAs Features and Benefits Advanced I/Os • 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation • Bank-Selectable I/O Voltages—up to 4 Banks per Chip • Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V

Contextual Info: Revision 13 IGLOO nano Low Power Flash FPGAs with Flash*Freeze Technology Features and Benefits High-Performance Routing Hierarchy Low Power Advanced I/Os • Segmented, Hierarchical Routing and Clock Structure • • • • • nanoPower Consumption—Industry’s Lowest Power

Contextual Info: Revision 10 ProASIC3 nano Flash FPGAs Features and Benefits Advanced I/Os • 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation • Bank-Selectable I/O Voltages—up to 4 Banks per Chip • Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V

Contextual Info: Revision 11 ProASIC3 nano Flash FPGAs Features and Benefits Advanced I/Os • 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation • Bank-Selectable I/O Voltages—up to 4 Banks per Chip • Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V

Contextual Info: Advance v0.3 ProASIC®3 nano Flash FPGAs Features and Benefits Advanced I/Os Wide Range of Features • 10 k to 250 k System Gates • Up to 36 kbits of True Dual-Port SRAM • Up to 71 User I/Os Reprogrammable Flash Technology • • • • 130-nm, 7-Layer Metal 6 Copper , Flash-Based CMOS Process

origin SEMICONDUCTOR

Contextual Info: IGLOO nano Handbook IGLOO nano Handbook Table of Contents Low-Power Flash Device Handbooks Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i Section I – IGLOO nano Datasheet IGLOO nano Low-Power Flash FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

A3P010

Contextual Info: Advance v0.2 ProASIC®3 nano Flash FPGAs Features and Benefits Advanced I/Os Wide Range of Features • 10 k to 250 k System Gates • Up to 36 kbits of True Dual-Port SRAM • Up to 71 User I/Os Reprogrammable Flash Technology • • • • 130-nm, 7-Layer Metal 6 Copper , Flash-Based CMOS Process

QN68

Abstract: VQ100 actel 0841 actel part markings
Contextual Info: Advance v0.6 ProASIC®3 nano Flash FPGAs Features and Benefits Advanced I/Os Wide Range of Features • 10 k to 250 k System Gates • Up to 36 kbits of True Dual-Port SRAM • Up to 71 User I/Os Reprogrammable Flash Technology • • • • 130-nm, 7-Layer Metal 6 Copper , Flash-Based CMOS Process

MARKING 9AB

Abstract: A3PN030Z A3PN250Z
Contextual Info: Revision 8 ProASIC3 nano Flash FPGAs Features and Benefits Advanced I/Os Wide Range of Features • 10 k to 250 k System Gates • Up to 36 kbits of True Dual-Port SRAM • Up to 71 User I/Os Reprogrammable Flash Technology • 130-nm, 7-Layer Metal 6 Copper , Flash-Based CMOS

actel date code

Contextual Info: Revision 8 ProASIC3 nano Flash FPGAs Features and Benefits Advanced I/Os Wide Range of Features • 10 k to 250 k System Gates • Up to 36 kbits of True Dual-Port SRAM • Up to 71 User I/Os Reprogrammable Flash Technology • 130-nm, 7-Layer Metal 6 Copper , Flash-Based CMOS

AGLN030Z

Abstract: AGLN010 AGLN250-Z AGLN060Z
Contextual Info: Revision 10 IGLOO nano Low Power Flash FPGAs with Flash*Freeze Technology Features and Benefits High-Performance Routing Hierarchy Low Power Advanced I/Os • Segmented, Hierarchical Routing and Clock Structure • • • • • nanoPower Consumption—Industry’s Lowest Power

IO39RSB2

Contextual Info: Revision 12 IGLOO nano Low Power Flash FPGAs with Flash*Freeze Technology Features and Benefits High-Performance Routing Hierarchy Low Power Advanced I/Os • Segmented, Hierarchical Routing and Clock Structure • • • • • nanoPower Consumption—Industry’s Lowest Power

AGLN010

Contextual Info: Advance v0.4 IGLOO nano Low-Power Flash FPGAs with Flash*Freeze Technology Features and Benefits Advanced I/Os • 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation • Bank-Selectable I/O Voltages—up to 4 Banks per Chip • Single-Ended I/O Standards: LVTTL, LVCMOS

AGLN030Z

Abstract: AGLN250Z AGLN250-Z c7160 CS81 QN68 VQ100 AGLN010
Contextual Info: Revision 11 IGLOO nano Low Power Flash FPGAs with Flash*Freeze Technology Features and Benefits High-Performance Routing Hierarchy Low Power Advanced I/Os • Segmented, Hierarchical Routing and Clock Structure • • • • • nanoPower Consumption—Industry’s Lowest Power

AGLN250Z1

Contextual Info: Revision 14 IGLOO nano Low Power Flash FPGAs with Flash*Freeze Technology Features and Benefits High-Performance Routing Hierarchy Low Power Advanced I/Os • Segmented, Hierarchical Routing and Clock Structure • • • • • nanoPower Consumption—Industry’s Lowest Power

Contextual Info: Revision 15 IGLOO nano Low Power Flash FPGAs with Flash*Freeze Technology Features and Benefits High-Performance Routing Hierarchy Low Power Advanced I/Os • Segmented, Hierarchical Routing and Clock Structure • • • • • nanoPower Consumption—Industry’s Lowest Power

AGLN010

Abstract: AGN060 JESD8-12A
Contextual Info: Advance v0.2 IGLOO nano Low-Power Flash FPGAs with Flash*Freeze Technology Features and Benefits Advanced I/Os • 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation • Bank-Selectable I/O Voltages—up to 4 Banks per Chip • Single-Ended I/O Standards: LVTTL, LVCMOS

LTC3025

Contextual Info: IGLOO nano Handbook IGLOO nano Handbook Table of Contents Low-Power Flash Device Handbooks Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i Section I – IGLOO nano Datasheet IGLOO nano Low-Power Flash FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I