INTEL SERIES GATE ARRAY Search Results

M5C060-45

Abstract: M5C060 E 817 271046 5CO60 M5C060-55
Contextual Info: INTEL inteT CORP UP/PRPHLS 1 EE D I I Mfl2 t>175 □ Q7 E 5 EÖ □ T - H L - 1 3 - 1 /7 M 5CO60 600 GATE CHMOS H-SERIES ERASABLE PROGRAMMABLE LOGIC DEVICE H-EPLD Military High Performance Upgrade for Commonly Used 24-Pin PLDs Programmable Clock System with Two

Robinson Nugent CATALOG

Abstract: MC68461 SAB80286 WE32104 Z80000 IMST414 FGE2000 MCA2800ALS 82786 intel TC110G
Contextual Info: T Circuit C o m p o n en ts Inc. r MicrofQ 3000 PGA Decoupling Capacitors Micro/Q 3000 ceramic capacitors are a family of very low inductance decoupling capacitors specifically designed to be through-hole mounted under pin grid arrays PGAs , PGA sockets, and

sharp schematic

Abstract: sharp display timing interface L296
Contextual Info: GATE ARRAYS AND CELL-BASED ICs SF-CAD ASIA ONLY The SF-CAD (Com puter-Aided Design) system is an IBM PC-compatible stand-alone gate array developm ent system. It integrates all the functions necessary for developing gate arrays form logic input to logic sim ulation. Based on SHARP'S "In-C ustom er Design Center" concept.

LS 7475

Abstract: 7475 D flip-flop 7475 TRANSPARENT LATCH EP1210 FLIP FLOP 7475 5C121 74HC 74hc xor gate PIN CONFIGURATION 7475 TTL 7475
Contextual Info: intei 5C121 1200 GATE CHMOS H-SERIES ERASABLE PROGRAMMABLE LOGIC DEVICE l Advanced Architecture Features Including Programmable Output Polarity Active High/Low , Register By-Pass and Reset Controls • High Performance LSI Semi-Custom Logic Replacement for Gate Arrays and

Contextual Info: in te l' M5C090 900 GATE CHMOS ERASABLE PROGRAMMABLE LOGIC DEVICE EPLD Military High Perform ance LSI Semicustom Logic Replacem ent fo r Low-End Gate Arrays TTL and 54HC SSI and MSI Logic Programmable Clock System with Tw o Synchronous Clocks as Well as

Contextual Info: intei M5C060 600 GATE CHMOS ERASABLE PROGRAMMABLE LOGIC DEVICE EPLD Military High Performance LSI Semicustom Logic Replacement for Low-End Gate Arrays TTL and 54HC SSI and MSI Logic Programmable Clock System with Two Synchronous Clocks as Well as Asynchronous Clocking Option on All

IBM schematics

Abstract: IBM PC AT schematics sharp schematic IBM PC schematics
Contextual Info: GATE ARRAYS AND CELL-BASED ICs I SF-CAD A SIA ONLY The SF-CAD (Com puter-Aided Design) system is an IBM PC-compatible stand-alone gate array developm ent system. It integrates all the functions necessary for developing gate arrays except automatic layout from logic input to logic simulation. Based on SHARP'S "InCustom er Design Center" concept SF-CAD helps customers efficiently develop their gate arrays in-house.

7475 d-flip flop

Abstract: LS 7475 7475 D latch 7475 data latch altera EP1210 FLIP FLOP 7475 PIN CONFIGURATION 7475 programmer EPLD Register 7475 EP1210
Contextual Info: intei 5C121 1200 GATE CHMOS H-SERIES ERASABLE PROGRAMMABLE LOGIC DEVICE l Advanced Architecture Features Including Programmable Output Polarity Active High/Low , Register By-Pass and Reset Controls High Performance LSI Semi-Custom Logic Replacement for Gate Arrays and

PLC88

Abstract: intel CMOS PLD intel PLD intel FPGA 29052 FX760
Contextual Info: int ! ÄO m iM ©! 0M F fô[iiflAT0®M ÌFX760 10 ns FLEXIogic FPGA WITH SRAM OPTION • High Performance FPGA (Field Programmable Gate Array — Deterministic 10 ns Pin-to-Pin Propagation Delays — 80 MHz System Clock Frequency Any CFB can be either 24V10 Logic or

intel FPGA

Abstract: FX730 intel PLD intel Series Gate Array IFX730 IC LM 317
Contextual Info: i n * ! O M F K iÆ Â ¥ D ® lM ÌFX730 10 ns FLEXIogic FPGA FAMILY WITH SRAM OPTION High Performance FPGA (Field Programmable Gate Array — Deterministic 10 ns Pin-to-Pin Propagation Delays — 80 MHz System Clock Frequency Any CFB Can Be Either 24V10 Logic or

Contextual Info: Product Brief January 2002 ORCA OR3LxxxB Series Field-Programmable Gate Arrays Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance, cost-effective, 0.25 µm 5-level metal technology. 2.5 V internal supply voltage and 3.3 V I/O supply voltage for speed and compatibility.

TRANSISTOR A30

Abstract: A30 TRANSISTOR Intel 8237A
Contextual Info: GFI2370A GFI2370A GFI2370A DMA CONTROLLER GENERAL DESCRIPTION : THE GFI2370A IS COMPATIBLE IN FUNCTIONALITY WITH THE INTEL 8237A 4-CHANNEL PROGRAMMABLE DMA CONTROLLER. THE PERFORMANCE IS MUCH IMPROVED OVER THE STANDARD PART. FOR A DETAILED FUNCTIONAL DESCRIPTION, SEE THE INTEL DATA BOOK.

28F008SC

Abstract: I960 hx 80960RP i960RP
Contextual Info: E TECHNICAL PAPER Interfacing the Byte-Wide SmartVoltage FlashFile Memory Family to the Intel960 Microprocessor Family October 1996 Order Number: 297804-001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or

LTC1307

Abstract: Flash Translation Layer XSR 28F160S5 F008 28F008S5 28F008SA 28F016S5 28F016SA 28F016SV 28F640J5
Contextual Info: E AP-647 APPLICATION NOTE 5 Volt Intel StrataFlash Memory Design Guide July 1999 Order Number: 292205-004 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of

bld386

Abstract: Specification 386 Object Modules Format 482991-002 XLINK386 BLD-386 omf-386 OH386 OMF386 IC386 object module format 386 PROM386
Contextual Info: Analysis Of Object File Formats For Embedded Systems Minda Zhang, Ph.D Senior software engineer Intel Corporation June, 1995 1. Introduction An object file format is the lowest level file format for any platform. It is designed with the primary goal of providing formatted binaries of machine codes, initialized data and uninitialized data for an

Contextual Info: in t e T 5C121 1200 GATE CHMOS H-SERIES ERASABLE PROGRAMMABLE LOGIC DEVICE Advanced Architecture Features Including Programmable Output Polarity Active High/Low , Register By-Pass and Reset Controls Programmable Clock System for Input Latches and Output Registers

intel FPGA

Abstract: intel PLD
Contextual Info: int ! ÌFX8160 10 ns FLEXIogic FPGA WITH SRAM OPTION High Performance FPGA Field Programmable Gate Array — Deterministic 10 ns Pin-to-Pin Propagation Delays — 80 MHz System Clock Frequency Electrically Erasable 0.6y, ETOX* IV CHMOS FLASH Technology

Contextual Info: Ä P Ä M g l D K 1 IF K 1 M 1 Ä T 0 ® M in te i ÌFX8160 10 ns FLEXIogic FPGA WITH SRAM OPTION High Performance FPGA Field Programmable Gate Array — Deterministic 10 ns Pin-to-Pin Propagation Delays — 80 MHz System Clock Frequency Electrically Erasable 0.6p, ETOX* IV

LUCENT 277

Abstract: ci 7495 intel FPGA CI LM 555
Contextual Info: Product Brief November 1999 ORCA OR3LxxxB Series Field-Programmable Gate Arrays Features • Abundant hierarchical routing resources based on routing two data nibbles and two control lines per set provide for faster place and route implementations and less routing delay.

Contextual Info: INTEL CORP MEMORY/PL] / böE D 4ß Sb l7 b GDflBDBfl 024 « I T L S A P m i M C B 0 M ( F [{ 3 R M ir 0 ® W In te l ) ÌFX8160 10 ns FLEXIogic FPGA WITH SRAM OPTION High Performance FPGA (Field Programmable Gate Array) — Deterministic 10 ns Pin-to-Pin

pcmcia flash card

Abstract: AB-56 AP-662 28F008S5 28F008SA 28F016S5 28F016SA INTEL application notes Intel AP MB245
Contextual Info: E AP-662 APPLICATION NOTE Migrating from Series 2+ to Value Series 100 PC Cards  for Systems Using Basic 28F008SA Command Set Programming Model June 1998 Order Number: 292220-001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or

flash memory vhdl code

Abstract: speedwave Viewlogic 28F001BX 28F002BC 28F002BX 28F010 28F020 28F200BX vhdl code memory
Contextual Info: COMPUTER-AIDED ENGINEERING TOOLS VIEWLOGIC SYSTEMS SpeedWave* • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete IEEE 1076 VHDL Complete interactive debugger Navigator for traversing the design hierarchy Context-sensitive help for ease of learning Imports EDIF netlists and

telematics control unit

Abstract: 8002-MC
Contextual Info: CarCube Within XILINX’ and ACUNIA jointly offer the CarCube™. CarCube™ is a reference design for in-car multimedia infotainment systems. This reference design is built on XINGU technology which is based on Xilinx’ Spartan II FPGA and the ® Intel Xscale™ Micro-architecture.

NFX780-15

Abstract: KUFX780-10 KUFX780 intel FPGA tms 1035 128x10 intel PLD NFX780-10 FX780 PROTEUS-UPLC88
Contextual Info: in te i P R S O B M A I f f if ÌFX780 10 ns FLEXIogic FPGA WITH SRAM OPTION High Performance FPGA Field Programmable Gate Array — Deterministic 10 ns Pin-to-Pin Propagation Delays — 80 MHz System Clock Frequency Any CFB can be either 24V10 Logic or