INTEL 80960KB PROGRAMMERS REFERENCE Search Results

TA80960KB

Abstract: 2T818 tl741
Contextual Info: intJ 80960KB EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped

TA80960KB

Abstract: 80960KA 80960KB 80960MC LAD1 12v
Contextual Info: 80960KB 80960KB EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT • High-Performance Embedded ■ Built-in Interrupt Controller Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache

ta80960kb

Abstract: LADI 12V VAX-11
Contextual Info: 80960KB EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING POINT UNIT • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped

Contextual Info: 80960KB EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING POINT UNIT • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ Built-In Interrupt Controller — 31 Priority Levels, 256 Vectors

Contextual Info: 80960KB EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING POINT UNIT High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz Built-In Interrupt Controller — 31 Priority Levels, 256 Vectors

Contextual Info: 5hE D • M fl2bl7S INTEL 011M07S CORP 402 ■ IT L 1 U P/PR PH LS 80960KA EMBEDDED 32-BIT PROCESSOR ■ Built-In Interrupt Controller — 32 Priority Levels 256 Vectors — 3.4 jlis Latency @ 25 MHz _ Easy to Use, High Bandwidth 32-Bit Bus — 66.7 Mbytes/s Burst

LAD19

Abstract: G101032 290192 ICE960
Contextual Info: IN T E L CORP in te i U P /P R P H L S 44E D a 4 fl2 b l7 S D IO IQ O S T E iIT L l; T = ^ ? - I 7 ~ s t 80960KA EMBEDDED 32-BIT PROCESSOR • High-Perform ance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 M IPS4 Sustained Execution at

Contextual Info: in te i i960 KA/KB PROCESSOR PRODUCT OVERVIEW INTRODUCTION This chapter provides an overview of the Intel i960 KB processor which is part of the i960 K series of embedded-processor products . All of the processors in the i960 K series of products are based on the Intel i960™ architecture. Most of the

80960KA

Abstract: 80960KB 80960MC TA80960KA pga 132 packaging
Contextual Info: 80960KA EMBEDDED 32-BIT MICROPROCESSOR • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped — Parallel Load/Decode for Uncached Instructions

80960KA

Abstract: 80960KB 80960MC 270775
Contextual Info: 80960KA EMBEDDED 32-BIT MICROPROCESSOR • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped — Parallel Load/Decode for Uncached Instructions

i960 Cx Instruction Set Quick Reference

Contextual Info: in t e i, 80960KA EMBEDDED 32-BIT MICROPROCESSOR • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped — Parallel Load/Decode for Uncached

Contextual Info: PRELIMINARY 80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT Commercial • High-Performance Embedded Architecture ■ — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■

a4490

Abstract: 80960MC LAD12 80960KA 80960KB M8259A i960 mc errata
Contextual Info: PRELIMINARY 80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT Commercial • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ On-Chip Floating Point Unit

Contextual Info: in te i 80960SA/80960SB EMBEDDED 32-BIT PROCESSORS WITH 16-BIT BURST DATA BUS High-Performance Embedded Architecture — 16 MIPS Burst Execution at 16 MHz — 5 MIPS* Sustained Execution at 16 MHz Built-In Interrupt Controller — 4 Direct Interrupt Pins — 32 Priority Levels 256 Vectors

Contextual Info: O M lF < § » Ä T D [ i i] in te i 80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT Military High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at

D15105

Abstract: 44fl5 271060 754for
Contextual Info: in te i 80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT Military High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS1 Sustained Execution at 25 MHz On-Chip Memory Management Unit

Contextual Info: intei 80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT Military On-Chip Memory Management Unit — 4 Gigabyte Virtual Address Space per Task — 4 Kbyte Pages with Supervisor/User Protection High-Performance Embedded

Contextual Info: Ä G S M A N G E O M [F iG M T D @ të 80960XA EMBEDDED 32-BIT MICROPROCESSOR WITH 33RD TAG BIT TO SUPPORT OBJECT-ORIENTED PROGRAMMING AND DATA SECURITY Military • On-Chip Memory Management Unit — 4 Gigabyte Linear Address Space per Task — 4 Kbyte Pages with Supervisor/User

cc196

Abstract: A-31 IEEE-695 ctools960 i960KB 80960KB Programmer Reference manual i960HA ASM96
Contextual Info:  i960 Processor Software Utilities User’s Guide Order Number: 485277-005 Revision Revision History Date -001 Original Issue. 12/92 -002 Minor corrections. 09/93 -003 Revised for CTOOLS960 R4.5 and GNU/960 R2.4. 05/94 -004 Revised for R5.0. 02/96 -005

IEEE695 specification

Abstract: IEEE-695 specification cc196 A-31 IEEE-695 80960KB Programmer Reference manual i960HA
Contextual Info: i960 Processor Software Utilities User's Guide Order Number: 485277-006 Revision Revision History Date -001 Original Issue. 12/92 -002 Minor corrections. 09/93 -003 Revised for CTOOLS960 R4.5 and GNU/960 R2.4. 05/94 -004 Revised for R5.0. 02/96 -005 Revised for R5.1.

gcu 101 setting manual

Abstract: cc196 ALL TYPE IC DATA AND manual substitution BOOK 80960KB Programmer Reference manual M-CORE Programmers Reference Manual GCC960 TLO32 i960 KB Processor gdb960
Contextual Info: i960 Processor Compiler User’s Manual Order Number: 651230-003 Revision Revision History Date 001 Initial Release. 02/96 002 Revised for release 5.1. 01/97 003 Revised for release 6.0. 12/97 In the United States, additional copies of this manual or other Intel literature may be obtained by writing:

gcu 101 setting manual

Abstract: cc196 GCC960 KX 001
Contextual Info: i960 Processor Compiler User's Guide Order Number: 651230-002 Revision Revision History Date -001 Original Issue. 02/96 -002 Revised for release 5.1 01/97 In the United States, Intel literature may be obtained by writing: Literature Distribution Center