INPUT AND GATE Search Results

smd cross reference

Abstract: 89551 5962-95681 95811 UT54ACS04 nand schmit trigger 54ac74 diode cross reference UT54ACS00 UT54ACS02
Contextual Info: RadHard MSI Logic SMD Cross Reference Description Part Number Quadruple 2-Input NAND Gates Quadruple 2-Input NOR Gates Hex Inverters Quadrupple 2-Input AND Gates Triple 3-Input NAND Gates Triple 3-Input AND Gates Hex Inverter Schmit Trigger Dual 4-Input NAND Gates

DM74LS51

Abstract: 54LS51DMQB 54LS51FMQB 54LS51LMQB DM74LS51M DM74LS51N E20A J14A M14A 54LS51
Contextual Info: DM74LS51 Dual 2-Wide 2-Input, 2-Wide 3-Input AND-OR-INVERT Gates Each package contains one 2-wide 2-input and one 2-wide 3-input AND-OR-INVERT gates. General Description This device contains two independent combinations of gates each of which performs the logic AND-OR-INVERT function.

DM74LS51

Abstract: AND-OR-INVERT 54LS51 54LS51DMQB 54LS51FMQB 54LS51LMQB DM74LS51M DM74LS51N E20A J14A
Contextual Info: 54LS51 DM74LS51 Dual 2-Wide 2-Input 2-Wide 3-Input AND-OR-INVERT Gates General Description This device contains two independent combinations of gates each of which performs the logic AND-OR-INVERT function Each package contains one 2-wide 2-input and one 2-wide 3-input AND-OR-INVERT gates

Contextual Info: 54ACTQ08 54ACTQ08 Quiet Series Quad 2-Input AND Gate Literature Number: SNOS581 54ACTQ08 Quiet Series Quad 2-Input AND Gate General Description The ’ACTQ08 contains four, 2-input AND gates and utilizes NSC Quiet Series technology to guarantee quiet output

HEF4001UBP

Abstract: 4001UB
Contextual Info: HEF4001UB gates QUADRUPLE 2-INPUT NOR GATE The HEF4001UB is a quadruple 2-input NOR gate. This unbuffered single stage version provides a direct implementation of the NOR function. The output impedance and output transition time depends on the input voltage and input rise and fall times applied.

all ic in one file

Abstract: EF4011
Contextual Info: HEF4011UB gates QUADRUPLE 2-INPUT NAND GATE: The HEF4011UB is a quadruple 2-input NAND gate. This unbuffered single stage version provides a direct implementation of the NAND function. The output impedance and ou :put transition time depends on the input voltage and input rise and fall times applied.

IDT74ALVC08

Abstract: ALVC08
Contextual Info: IDT74ALVC08 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-AND GATE EXTENDED COMMERCIAL TEMPERATURE RANGE IDT74ALVC08 ADVANCE INFORMATION 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-AND GATE DESCRIPTION: FEATURES: This quadruple 2-input positive-AND gate is built using advanced

AO222

Abstract: SL 220 AO211 AO22
Contextual Info: LOGIC CELLS Cell Names & Function Descriptions Cell Name Function Description AD2 2-Input AND with 1X Drive AD2D2 2-Input AND with 2X Drive AD2D4 2-Input AND with 4X Drive AD2D8 2-Input AND with 8X Drive AD2B 2-Input AND with one Inverted Input, 1X Drive AD2BD2

TC4011UB

Abstract: TC4011UBP 2 input nand gate 18v TC4001UBP
Contextual Info: TC4001UBP, TC4011UBP/UBFN C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC _ TC4001UB QUAD 2 INPUT NOR GATE TC4011UB QUAD 2 INPUT NAND GATE_ TC4001UB and TC4011UB are 2 input NOR gate and 2 input NAND gate respectively. The pin connections are same as

pin diagram of CD4081

Abstract: ic CD4081 pin diagram ic cd4081 CD4081 CD4073B CD4073BMS CD4081B CD4081BMS CD4082BMS
Contextual Info: CD4073BMS, CD4081BMS CD4082BMS Semiconductor CMOS AND Gate January 1993 Features Pinout High-Voltage Types 20V Rating CD4073BM S TOP VIEW CD4073BMS Triple 3-Input AND Gate CD4081BMS Quad 2-Input AND Gate KJ a CD4082BMS Dual 4-Input AND Gate Medium Speed Operation:

AO211

Abstract: AO22 ao21
Contextual Info: LOGIC CELLS Cell Names & Function Descriptions Cell Name Function Description AD2_LP 2-Input AND with 1X Drive AD2D2_LP 2-Input AND with 2X Drive AD2D4_LP 2-Input AND with 4X Drive AD2D8_LP 2-Input AND with 8X Drive AD2B_LP 2-Input AND with one Inverted Input, 1X Drive

hef4001

Abstract: l6530 HEF4001UBP
Contextual Info: HEF4001UB ^ _ QUADRUPLE 2-INPUT NOR GATE The HEF4001UB is a quadruple 2-input NOR gate. This unbuffered single staije version provides a direct implementation o f the NOR function. The ou tput impedance and output transition tim e depends on the input voltage and input rise and fall times applied.

TC4082B

Abstract: TC4082BP TC4073BP TC4081B
Contextual Info: C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC4073BP/BF/BFNJC4081BP/BF/BFN TC4082BP TC4073B TRIPLE 3 INPUT AND GATE TC4Q81B QUAD 2 INPUT AND GATE TC4082B DUAL 4 INPUT AND GATE TC4081BP, TC4073B and TC4082B are positive logic AND gates w ith tw o inputs, three inputs and fo ur inputs

tc4082bp

Abstract: TC4073BP
Contextual Info: TC4073BP/BF/BFN, TC4081BP/BF/BFN C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC4082BP TC4073B TRIPLE 3 INPUT AND GATE TC4081B QUAD 2 INPUT AND GATE TC4082B DUAL 4 INPUT AND GATE TC4081 BP, TC4073B and TC4082B are positive logic AND gates with tw o inputs, three inputs and four inputs

74F11

Abstract: 74F10 N74F10D N74F10N N74F11D N74F11N
Contextual Info: INTEGRATED CIRCUITS 74F10 Triple 3-input NAND gate 74F11 Triple 3-input AND gate Product specification IC15 Data Handbook Philips Semiconductors 1989 Sep 20 Philips Semiconductors Product specification Gates 74F10, 74F11 74F10 Triple 3-input NAND gate 74F11 Triple 3-input AND gate

circuit diagram of 7436 ic

Abstract: CD4073B CD4073BMS CD4081B CD4081BMS CD4082B CD4082BMS nor gate 7433
Contextual Info: CD4073BMS, CD4081BMS CD4082BMS CMOS AND Gate January 1993 Features Pinout • High-Voltage Types 20V Rating CD4073BMS TOP VIEW • CD4073BMS Triple 3-Input AND Gate • CD4081BMS Quad 2-Input AND Gate • CD4082BMS Dual 4-Input AND Gate • Medium Speed Operation:

circuit diagram of 7436 ic

Abstract: CD4073B CD4073BMS CD4081B CD4081BMS CD4082B CD4082BMS
Contextual Info: CD4073BMS, CD4081BMS CD4082BMS CMOS AND Gate January 1993 Features Pinout • High-Voltage Types 20V Rating CD4073BMS TOP VIEW • CD4073BMS Triple 3-Input AND Gate • CD4081BMS Quad 2-Input AND Gate • CD4082BMS Dual 4-Input AND Gate • Medium Speed Operation:

2-input & 3-input AND-OR-invert Gate

Abstract: 74F51 N74F51D N74F51N
Contextual Info: INTEGRATED CIRCUITS 74F51 Dual 2-wide 2-input, 2-wise 3-input AND-OR-invert gate Product specification IC15 Data Handbook Philips Semiconductors 1989 Mar 03 Philips Semiconductors Product specification Dual 2-wide 2-input, 2-wide 3-input AND-OR-invert gate

Contextual Info: 4081B 4082B 4073B INTERNATIONAL, INC CMOS AND GATES 4081B - Quad 2-Input AND 4082B • Dual 4-Input AND 4073B - Triple 3-Input AND CONNECTION DIAGRAMS all packages FEA TU R ES 4 4 4 Buffered Outputs Diode Protection on all Inputs Fully "B"-Series Compatible

BU4081B

Abstract: BU4081BF BU4081BFV SSOP-B14
Contextual Info: Standard ICs Quad 2-input AND gate BU4081B / BU4081BF / BU4081BFV The BU4081B, BU4081BF, and BU4081BFV are dual-input positive-logic AND gates with four circuits mounted on a single chip. An inverter-type buffer is added to the gate output, improving input / output transmission speed, and an

BU4081B

Abstract: BU4081BF BU4081BFV SSOP-B14
Contextual Info: Standard ICs Quad 2-input AND gate BU4081B / BU4081BF / BU4081BFV The BU4081B, BU4081BF, and BU4081BFV are dual-input positive-logic AND gates with four circuits mounted on a single chip. An inverter-type buffer is added to the gate output, improving input / output transmission speed, and an

74AHCT1G08GV

Abstract: 74AHC1G08 74AHC1G08GV 74AHC1G08GW 74AHCT1G08 74AHCT1G08GW JESD22-A114E SOT753 08 SOT353-1 Package
Contextual Info: 74AHC1G08; 74AHCT1G08 2-input AND gate Product data sheet 1. General description 74AHC1G08 and 74AHCT1G08 are high-speed Si-gate CMOS devices. They provide a 2-input AND function. The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V.

Contextual Info: LS TTL DN74LS Series DN74LS51 DN74LS51 bo 741*51 2-w ide 3-input, 2-w ide 2-input AND-OR-INVERT Gates • Description DN74LS51 contains tw o 2-input and tw o 3-input AND-ORINVERT gates. ■ Features • • • • Low pow er consum ption P d = 5.5mW typical

Contextual Info: TC4S81F TOSHIBA C MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 2 INPUT AND GATE Tile TC4S81P contains S-input positive logic AND gates. Gate output with inverter buffer improves the input-output characteristics and if the load capacitance increases, it can stop any changes