INITIALIZATION Search Results

MiFare DESFire EV1 8k

Abstract: Mifare protocol AN10833 AN 130830 AN-130830 Mifare plus Mifare Desfire protocol Mifare plus protocol Mifare Plus X 4K UID 7 Byte Mifare ultralight C
Contextual Info: AN10833 MIFARE Type Identification Procedure Rev. 3.0 — 18 May 2009 018430 Application note PUBLIC Document information Info Content Keywords MIFARE, ISO/IEC 14443 Abstract This document describes how to differentiate between the members of the MIFARE card IC family. ISO/IEC 14443-3 describes the initialization

AK8975

Abstract: BMP085 Bosch BMP085 magnetometer ak8975 ITG-3200 AK8957 AKM AK8975 BMA150 gyroscope bosch atmel 924
Contextual Info: AVR4016: Sensors Xplained Software Users Guide Features • • • • Hardware-independent C language interfaces for sensor devices Conversion to standard units for all measurement types Device drivers for a variety of MEMS-based sensors Easy-to-use configuration and initialization

DIAGRAM pal 005a

Abstract: pal 005a
Contextual Info: Preliminary a COM’L PAL24R10-10 Series Advanced Micro Devices 10 ns 28-pin TTL Programmable Array Logic DISTINCTIVE CHARACTERISTICS • 10 ns m axim um propagation delay Power-up reset for initialization ■ f MAx = 55.5 MHz Register preload for testability

30C162

Abstract: 12x10 character TRANSISTOR SMD MARKING CODE kh "character rom" siemens S43 SMD marking code AE SMD Transistor siemens flash smd marking KH 235L P-LCC-68-1
Contextual Info: MEGATEXT and MEGATEXT PLUS ICs SDA 5273 / SDA 5275 SDA 5273-2 / SDA 5275-2 Revision History: 06.97 Previous Releases: 11.96 Page Subjects changes since last revision 20 Now also covers SDA 5275-2 and SDA 5273-2 versions; Reset/chip initialization update

Si8421A

Abstract: Si8420B Si8421B Si8410B Si8410 Si8420 Si8421 VDE0884 SI8420-B-IS Si8420-B
Contextual Info: Si8410/20/21 S INGLE A N D D UAL -C HANNEL D IGITAL I SOLATORS Features High-speed operation Pin Assignments 2500 VRMS isolation DC – 150 Mbps Narrow Body SOIC Transient Immunity Low propagation delay >25 kV/µs <10 ns DC correct No start-up initialization required

Contextual Info: CDCF5801A www.ti.com SCAS816 – MARCH 2006 CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT FEATURES • • • • • • • • • • • • • Low-Jitter Clock Multiplier: x1, ×2, ×4, ×8 Fail-Safe Power Up Initialization Programmable Bidirectional Delay Steps of

sy6520

Abstract: pia 6820 sy6820 MC6820 PIA 6820 PIA D6520 pia MC6820 SY6520a mc6820 Synertek
Contextual Info: SY6520/SY6520A SY6820/SY68B20 Peripheral Interface Adapter PIA Features Autom atic "Handshake" Control of Data Transfers Programmable Interrupt Capability Autom atic Initialization on Power Up 1 and 2 MHz Versions • Direct Replacement for M C6820 • Single +5V Power Supply

Contextual Info: April 4, 2013 C8051F41x Revisions A-F Errata Hardware Errata Erratum # H1 H2 H3 Title XTLVLD is Incorrect Port Pin Overvoltage Clock Glitch During the Clock Multiplier Initialization Sequence Impact Minor Minor Minor Status Affected Revisions Fixed Revision

M52235EVB

Abstract: Bean tn265 M5222
Contextual Info: Technical Note TN265 Using the Device Initialization and Processor Expert with CodeWarrior Development Studio for ColdFire Architectures v7.0 By: Alfredo Soto and Oscar Gueta Introduction This document demonstrates using Processor Expert embedded beans for a ColdFire microcontroller

Si8420

Abstract: Si8410 Si8421 VDE0884 SI8410-C-IS
Contextual Info: Si8410/20/21 S INGLE & D UAL - C HANNEL D IGITAL I SOLATORS Features High-speed operation Pin Assignments 2500 VRMS isolation DC – 150 Mbps Narrow Body SOIC Transient Immunity Low propagation delay >25 kV/µs <10 ns DC correct No start-up initialization required

Contextual Info: Preliminary COM’L Cl PAL24R10-10 Series Advanced Micro Devices 10 ns 28-pin TTL Programmable Array Logic DISTINCTIVE CHARACTERISTICS Power-up reset for initialization • 10 ns maximum propagation delay ■ f MA x ■ 8 ns maximum from clock input to data output

Contextual Info: ESMT M13S128168A Operation temperature condition -40°C~85°C Revision History Revision 1.0 03 Jan. 2007 - Original Revision 1.1 (19 Mar. 2008) - Add BGA package - Modify the waveform of Power up & Initialization Sequence - Modify the θ value of TSOPII package dimension

MC68HC11

Abstract: EB292 M68HC11EVBU MC68HC11EVBU DSA003656 Buffalo monitor
Contextual Info: Order this document by EB292/D Motorola Semiconductor Engineering Bulletin EB292 Initialization Considerations When Moving from the BUFFALO Monitor to a Standalone MC68HC11 By Janet M. Snyder Austin, Texas General Information Analog-to-digital A/D convertor code written under the BUFFALO

Contextual Info: ATS415 Features • Pin-for-PIn Compatible, Functional Superset of PLS1 OS/A and PLUS405 Logic Sequencers • Zero Standby Power of Less than 100 nA Worst Case Power Dissipation at fMAX = 80 mA (Worst Case) • CM OS and TTL Compatible • Programmable Asynchronous Initialization and OE Functions

XC17000

Abstract: XC3000 XC4000 XC2000 XC3000A XC3100 XC3100A XC4000A XC4000D XC4000H
Contextual Info: Configuration Control Pin Connections in T 36 he following recommendations guarantee a well-defined beginning for any FPGA configuration or reconfiguration process — after the initialization and clearing of the configuration memory in all FPGAs has been completed, and the

transistor c380

Abstract: Motorola MPC556 transistor c388 c1781 DE C308 mpc556 transistor c114 diagram transistor c114 diagrams transistor c118 transistor c144
Contextual Info: SECTION 5 UNIFIED SYSTEM INTERFACE UNIT The unified system interface unit USIU of the MPC555 / MPC556 controls system start-up, system initialization and operation, system protection, and the external system bus. The MPC555 / MPC556 USIU functions include the following:

AVR block diagram

Abstract: AT94K codevision
Contextual Info: AVR-FPGA Interface Design 2 Features • Initialization and Use of AVR-FPGA Interface and Interrupts • Initialization and Use of the Shared Dual-port SRAM • Full Source Code for AVR Microcontroller and FPGA Included Programmable SLI AT94K Description

Contextual Info: Si8410/20/21 5 kV Si8422/23 (2.5 & 5 kV) L O W - P OWER, S INGLE AND D U A L - C HANNEL D IGITA L I S O L A T O R S Features  High-speed operation DC to 150 Mbps  No start-up initialization required  Wide Operating Supply Voltage: 2.6–5.5 V

PAL20L8

Abstract: MMI PAL 20R4 mmi pal20l8 PAL20R4 MMI TOP MARKING amd part marking PAL20R6 PAL20L8 mmi AMD PAL20L8 LA4490
Contextual Info: COM’L: -5/7/B/B-2/A, 10/2 a MIL: -10/12/15/B/A Advanced Micro Devices PAL20R8 Family 24-Pin TTL Programmable Array Logic D ISTINCTIVE CHARACTERISTICS • As fast as 5 ns maximum propagation delay ■ Power-up reset for initialization ■ Popular 24-pin architectures: 20L8,20R8,

53DA441

Abstract: 53DA442 63DA441 63DA442 D442 Monolithic Memories PROM programming MONOLITHIC MEMORIES PROM
Contextual Info: 1 0 2 4 x 4 Diagnostic Registered PROM 5 3 /6 3 D A 4 4 1 5 3 /6 3 D A 4 4 2 Enables and Output Initialization Features/Benefits • Programmable asynchronous output initialization • Three-state outputs with two enables • Provides system diagnostic testing with system

53DA841

Abstract: 63DA841
Contextual Info: 2 0 4 8 x 4 Diagnostic Registered PROM 53D A 841 63D A 841 w ith Asynchronous Enable and Output Initialization Features/Benefits Description • Asynchronous output enable • Programmable asynchronous output Initialization • Provides system diagnostic testing with system

DS2151

Abstract: DS2153
Contextual Info: DS2151/53 APPLICATION NOTE Programming, Initialization March 12, 1996 GENERAL INITIALIZATION FOR THE DS2151 AND DS2153 After power-up, when supplies and clocks have stabilized, internal registers must be initialized. It is a good idea to clear, set to 00H, ALL R/W registers. Certain registers have bits which control special test modes and features which

AVR block diagram

Abstract: AT94K atmel AT94K
Contextual Info: AVR-FPGA Interface Design 1 Features • Initialization and Use of AVR-FPGA Interface and Interrupts • Full Source Code for AVR Microcontroller and FPGA Included Description Atmel’s AT94K sample designs are provided to familiarize the user with the AT94K

DSA00359816

Abstract: AT94K 32 Bit loadable counter
Contextual Info: AVR-FPGA Interface Design 3 Features • Initialization and Use of AVR-FPGA Interface and Interrupts • Initialization and Use of the Shared Dual-port SRAM • Full Source Code for AVR Microcontroller and FPGA Included Programmable SLI AT94K Description