IKOS SYSTEMS Search Results

XC4000

Abstract: JAEGER
Contextual Info: XC4000 FPGA Provides IKOS with Increased Capacity for Third-Generation Emulator Page 1 of 2 Customer Success - IKOS XC4000 FPGA Provides IKOS with Increased Capacity for Third-Generation Emulator "Because it is a high density, high capacity device, the Xilinx FPGA allows us to provide very large capacity

ic 74151

Abstract: pin configuration IC 74151 MSM10S0000 MSM10S0050 MSM10S0110 MSM10S0210 MSM10S0300 MSM10S0570 MSM10S0980 base cell
Contextual Info: DATA SHEET O K I A S I C P R O D U C T S MSM10S0000 0.8 µm Sea of Gates Family 3-V and 5-V Applications December 1997 TRADEMARKS DAZIX and Advansys are trademarks of Intergraph, Inc. IKOS is a trademark of IKOS Systems, Inc. Mentor Graphics, Parade and Idea are trademarks of Mentor Graphics Corporation

XC5200

Contextual Info: Edway Design Systems System Explorer ASIC Explorer XILLAS Concept Composer Verilog FPGA Designer Synergy Design Works TimingDesigner ALPS LSI Technologies Aptix Corporation Logical Devices Mentor Graphics ITS Logic Modeling Corp. Synopsis Division INCASES Engineering

144 QFP body size

Abstract: 35x35 bga BGA and QFP Package vhdl code for usart DesignWare SPI 0.18-um CMOS technology characteristics ARM7 verilog code NEC-V850 PZT driver design vhdl coding for analog to digital converter
Contextual Info: GS20 0.18-µm CMOS Standard Cell/Gate Array Version 1.0 April 6, 1999 Copyright  Texas Instruments Incorporated, 1999 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the

verilog code for 32 bit risc processor

Abstract: vhdl code for usart 35x35 bga Sun Enterprise 250 Sun Ultra 30 DesignWare SPI 0.18 um CMOS free vhdl code download for usart NEC-V850 PZT driver design
Contextual Info: GS30TR 0.15-µm CMOS Standard Cell/Gate Array Version 1.0 September 23, 1999 Copyright  Texas Instruments Incorporated, 1999 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the

ahb arbiter in mentor

Abstract: 16x16x1.4
Contextual Info: GS40 0.11-µm CMOS Standard Cell/Gate Array Version 0.5 May 19, 2000 Copyright  Texas Instruments Incorporated, 2000 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the

38S02

Abstract: ipad data sheet MSM38S0000 MSM98S MSM98S000
Contextual Info: DATA SHEET O K I A S I C P R O D U C T S 0.8µm Mixed 3-V/5-V MSM38S0000 Sea of Gates and MSM98S000 Customer Structured Arrays February 1995 TRADEMARKS AIX, DOS, PC, and Windows are trademarks, and IBM is a registered trademark of IBM Corporation Apollo, Domain, and DomainOS are trademarks of Apollo Computer, a subsidiary of Hewlett-Packard

verilog code for UART with BIST capability

Abstract: VHDL CODE FOR HDLC controller ARM dual port SRAM compiler DesignWare SPI vhdl code for watchdog timer of ATM vhdl coding for analog to digital converter Sun Enterprise 250 static SRAM single-port verilog code for 16 bit risc processor verilog code arm processor
Contextual Info: GS30 0.15-µm CMOS Standard Cell/Gate Array Version 0.2 May 16, 2000 Copyright  Texas Instruments Incorporated, 2000 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the

34992

Abstract: SSC5100 F232-10 pinpad 78568
Contextual Info: S-n 0 S SYSTEMS INC 5bE D • 7 cï 3 S tl D c1 G ODI Sb b SSC5000 'Ib? M S MO Series 0.8u HIGH SPEED CMOS STANDARD CELL SERIES° 7 ■ DESCRIPTION The S-MOS SSC5000 standard cell series is a 0.8 micron drawn family of standard cell circuits. It is manufactured on S-MOS’ state-of-the-art 0.8 micron double-metal N-well CMOS process. It Is comprised of 20

TOSHIBA TC160G

Abstract: Toshiba NAND 67 Bga 568ps tc160g TC190G04 tc170g TC190G TC190G02 TC190G10 C2878
Contextual Info: TOSHIBA System ASIC TC190 Series CMOS ASICs 0.6µ 3.0/3.3V ASIC Family The 0.6µm, 5V TC190 ASIC series provides higher system performance and device integration with lower power than previous generation 5V families. Highly accurate delay models, area efficient memory cells and a very fine pitch TAB bonding capability

toshiba TC200

Abstract: toshiba TC200C TOSHIBA GATE ARRAY Toshiba BGA 224 TC200E TC200 TC200C02 TC200G Edison time delay TC180
Contextual Info: TOSHIBA System ASIC TC200 Series CMOS ASICs 0.4µ 3.0/3.3V ASIC Family The TC200 series is a family of 0.4µm, 3.0/3.3V ASICs. They are the first of a new generation of deep sub-micron “System ASIC” products with highly accurate delay models, area efficient memory cells and a very fine pitch TAB bonding capability for high

verilog code voltage regulator

Abstract: verilog code for 32 bit risc processor vhdl code for watchdog timer of ATM fastscan verilog code for 16 bit risc processor NET 1672 analog to digital converter verilog Multi-Channel DMA Controller verilog code arm processor Texas Instruments I2C
Contextual Info: GS30TR 0.15-µm CMOS Standard Cell/Gate Array Version 1.2 May 17, 2000 Copyright  Texas Instruments Incorporated, 2000 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the

synopsys Platform Architect

Abstract: clock tree balancing DesignWare SPI vhdl code for watchdog timer of ATM 0.18-um CMOS technology characteristics vhdl coding for analog to digital converter CML Vterm 27x27
Contextual Info: GS20 0.18-µm CMOS Standard Cell/Gate Array Version 1.1 May 19, 2000 Copyright  Texas Instruments Incorporated, 2000 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the

verilog code for UART with BIST capability

Abstract: vhdl code for 8 to 3 encoder using concurrent sta 2 port register file open LVDS deserialization IP OC768 ARM10 ARM946 SR40 TLK2201 verilog code for ahb bus slave
Contextual Info: SR40 0.095-µm High-Speed Copper Standard Cell/Gate Array ASIC Version 1.1 May 17, 2001 Copyright  Texas Instruments Incorporated, 2001 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the

Contextual Info: Oki Semiconductor MSM13Q/14Q 0.35 |im Sea of Gates Arrays DESCRIPTION Oki's 0.3 5 Jim ASIC products deliver ultra-high performance and high density at low power dissipation. The M SM 13Q0000/14Q0000 series devices referred to as "M SM 13Q /14Q " are implemented with the

altera library pld

Contextual Info: EDA Software Support January 1998. ver. 7 Introduction ACCESS*" PROGRAM Seamless design flow and high-quality integration of third party EDA tools are essential to the continued success of programmable logic devices PLDs . Thus, Altera has established the Altera Commitment to

Behavioral verilog model

Abstract: transistor 0882 5551 datasheet F 9016 transistor
Contextual Info: EDA Software Support November 1998, ver. 7.01 Introduction Seamless design flow and high-quality integration of third party EDA tools are essential to the continued success of programmable logic devices PLDs . Thus, Altera has established the Altera Commitment to

MSM13Q

Abstract: base cell floorplan io uart vhdl
Contextual Info: DATA SHEET O K I A S I C P R O D U C T S MSM13Q/14Q000 0.35 µm Sea of Gates Arrays November 1999 • ■ –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––

Contextual Info: DATA SHEET O K I A S I C P R O D U C T S MG113P/114P/115P/73P/74P/75P 0.25µm Sea of Gates and Customer Structured Arrays March 1998 MG113P/114P/115P/73P/74P/75P 0.25µm Sea of Gates and Customer Structured Arrays DESCRIPTION Oki’s 0.25µm Application-Specific Integrated Circuit ASIC products are available in both Sea Of Gates

Contextual Info: •SSSS D a t a S h e e t _ O K I A S I C P R O D U PmgOoDDOOBDg ^ MG113P/114P/115P/73P/74P/75P 0.25|im Sea of Gates and Customer Structured Arrays March 1998 Oki Semiconductor Oki Semiconductor MG113P/114P/115P/73P/74P/75P 0.25|im Sea of Gates and Customer Structured Arrays

SUN HOLD 0910

Contextual Info: Oki Semiconductor MSM32Q/33Q/98Q/99Q 0.35 |im Sea of Gates and Customer Structured Arrays DESCRIPTION Oki's 0.35 Jim Application-Specific Integrated Circuit ASIC products are available in both Sea Of Gates (SOG) and Customer Structured Array (CSA) architectures. Both the SOG-based MSM33Q0000 series and

1117 transistor 0340 180

Abstract: M13Q floorplan io uart vhdl MSM13Q
Contextual Info: MSM13/14Q 35µm DS 9…9/14Backup Page -1 Friday, November 21, 1997 11.17 a DATA SHEET O K I A S I C P R O D U C T S MSM13Q0000/14Q0000 0.35 µm Sea of Gates Arrays November 1997 MSM13/14Q 35µm DS 9…9/14Backup Page 0 Friday, November 21, 1997 11.17 a MSM13/14Q 35µm DS 9…9/14Backup Page 1 Friday, November 21, 1997 11.17 a

oki cross

Abstract: MG63P MG64P MG65P b0268
Contextual Info: DATA SHEET O K I A S I C P R O D U C T S MG63P/64P/65P 0.25µm Embedded DRAM/ Customer Structured Arrays November 1998 MG63P/64P/65P 0.25µm Embedded DRAM/Customer Structured Arrays DESCRIPTION Oki’s 0.25 µm MG63P/64P/65P Application-Specific Integrated Circuit ASIC provides the ability to

TI 35X35 BGA 368 BGA

Abstract: 547 B34 kl 668 sem 304
Contextual Info: •SSSS D a t a S h e e t _ O K I A S I C P R O D U MG73Q000/74Q000 and MSM98Q000/99Q000 0.35iim Customer Structured Arrays April 1999 Oki Semiconductor CONTENTS D