IDT7321 Search Results

tag 9035

Abstract: 9035 tag 2s94 4 bit odd parity checker using XOR AND XOR COMPLEMENT 25944
Contextual Info: IDT7321OA/11A d t) Data B o o k A, S e c t i o n 5.9, P a g e 1 FAST CMOS OCTAL REGISTER TRANSCEIVER WITH PARITY PRELIMINARY IDT73210/A IDT73211/A Integrated Devi ce Technology, Inc. FEATURES • Tw o bidirectional interfacing ports • Single-level pipeline register for one port and one-level

Contextual Info: lljljfiv Integrated DeviœTèchnology. Inc PRELIMINARY IDT 7320 IDT 7321 16-BIT CMOS MULTILEVEL PIPELINE REGISTERS FEATURES: DESCRIPTION • IDT7320: E ig h t 16-bit h ig h -sp e e d p ip e lin e registers • IDT7321: S even 16-bit h ig h -s p e e d p ip e lin e re giste rs p lu s a

2594

Abstract: 4-bit even parity checker circuit diagram XOR
Contextual Info: \dt Integrated Device Technology, Inc. FEATURES • • • • • PRELIMINARY IDT73210/A/B IDT73211/A/B FAST CMOS OCTAL REGISTER TRANSCEIVER WITH PARITY 73210/211 Single-level pipeline register from Port A to Port B 73210 Two level pipeline register from Port B to Port A

tag 9035

Abstract: 9035 tag 2594 dc/Triac/TRIAC tag 9035
Contextual Info: Integrated Device Technology, Inc. FAST CMOS OCTAL REGISTER TRANSCEIVER WITH PARITY FEATURES • • • • • PRELIMINARY IDT73210/A/B IDT73211/A/B • 73210/211 Single-level pipeline register from Port A to Port B • 73210 Two level pipeline register from Port B to Port A

Contextual Info: FAST CMOS OCTAL REGISTER TRANSCEIVER WITH PARITY Integrated Device Technology, Inc* FEATURES PRELIMINARY IDT73210/A/B IDT73211/A/B 73210/211 Single-level pipeline register from Port A to Port B 73210 Two level pipeline register from Port B to Port A 73211 Single level pipeline register from Port B to Port A

74FCT520

Abstract: IDT79R4000 IDT73200 MIPS R4000 R3000 R3051 R3052 R3081 R4000 mips r4000 block diagram
Contextual Info: DESIGNING READ AND WRITE BUFFERS FOR THE R4000 SYSTEM INTERFACE APPLICATION NOTE AN-114 Integrated Device Technology, Inc. By Andrew Ng INTRODUCTION THE R4000 MICROPROCESSOR This article describes the basic concepts behind designing with the IDT79R4000 System Interface. The System Interface

D431S

Abstract: IDT7320
Contextual Info: INTEGRATE» DEVICE IME D • 4 0 25 7 7 1 D Q D 3 Ö 47 2 PRELIMINARY IDT 7320 IDT 7321 16-BIT CMOS ' . MULTILEVEL PIPELINE REGISTERS DESCRIPTION FEATURES: • 12ns to 20ns access time • Programmable multilevel register configurations • Powerful instruction set: transfer, hold, load directly