IDOE23 Search Results

Contextual Info: 82355 9.0 DETAILED PIN DESCRIPTION 9.1 EISA Interface Signals Pin Name Description START# I/O TRI-STATED EISA CYCLE START STROBE The START# signal provides timing control at the start of a cycle. During EISA master mode, the BMIC drives this signal low after LA <31:2> and M /IO become valid and negates

XC96

Abstract: XC87 82355 XC8F XC89 EISA chip set XC90
Contextual Info: 82355 13.0 BMIC PN AND PACKAGE INFORMATION 13.1 Signal Overview Name = Pin Name, Type = I— Input, O—Output, OC— Open Collector, B— Both Input and Output, BC— Both and Open Collector, Pin = Pin Location Name Type Pin Description EISA BUS INTERFACE SIGNALS

82358

Abstract: XC96 8251 intel microcontroller architecture F245B intel 82358 INTERFACING OF 8272 WITH 8086 EISA chip set 82355 ta 8271 hq intel 82355
Contextual Info: 82355 BUS MASTER INTERFACE CONTROLLER BMIC • Designed fo r use in 32-Bit EISA Bus Master Expansion Board Designs — Integrates Three interfaces (EISA, Local CPU, and Transfer Buffer) ■ Supports 16- and 32-Bit Burst Transfers — 33 M b ytes/S ec Maximum Data

Contextual Info: inter P B IIU IIM IIIN IÄ IB V 82355 11.0 D.C. SPECIFICATIONS NOTICE: This data sheet contains preliminary infor­ mation on new products in production. The specifica­ tions are subject to change without notice. 11.1 Maximum Ratings* * WARNING: Stressing the device beyond the “Absolute

XC90

Abstract: intel 82358
Contextual Info: 82355 BUS MASTER INTERFACE CONTROLLER BMIC • Designed for use in 32-Bit EISA Bus Master Expansion Board Designs — Integrates Three interfaces (EISA, Local CPU, and Transfer Buffer) ■ Supports 16- and 32-Bit Burst Transfers — 33 Mbytes/Sec Maximum Data

XC90

Contextual Info: in tj 82355 BUS MASTER INTERFACE CONTROLLER BMIC • Designed for use in 32-Bit EISA Bus Master Expansion Board Designs — Integrates Three Interfaces (EISA, Local CPU, and Transfer Buffer) ■ Supports 16- and 32-Bit Burst Transfers — 33 Mbytes/Sec Maximum Data