IDD33 Search Results

SANDISK NAND ID code

Abstract: Sandisk Flash ChipSet
Contextual Info: White Electronic Designs IDD33, IDD38 SERIES DirectDrives IDD33, IDD38 SERIES DirectDrives INTRODUCTION n - 1 non-recoverable error in 1014 bits read IDD33 and IDD38 are families of solid-state Flash Disk Modules IDE drives with either standard 44-pin connectors or standard 40-pin connectors. They are nonvolatile, mass-memory storage devices, ideal for mobile computing and industrial applications – everywhere

VTXP-6

Abstract: TXC-06951 g803 Motorola 0X69 TXC-06951-MB 98822
Contextual Info: VTXP-6 Device STM-1/STS-3 SDH/SONET TU/VT Processor and Cross Connect TXC-06951 DATA SHEET PRELIMINARY TXC-06951-MB, Ed. 5 March 2006 FEATURES APPLICATIONS • Supports two line ports using the standard byte wide 19.44 MHz Telecom Bus, or a single line port using the standard byte wide 77.76 MHz Telecom Bus.

CP-1201

Abstract: DIX4192 SRC4382 SRC4392IPFBR SRC4392IPFBT TQFP-48
Contextual Info: BurrĆBrown Products from Texas Instruments SR C4 392 SRC4392 SBFS029C – DECEMBER 2005 – REVISED SEPTEMBER 2007 Two-Channel, Asynchronous Sample Rate Converter with Integrated Digital Audio Interface Receiver and Transmitter FEATURES 1 • Two-Channel Asynchronous Sample Rate

IS61QDB22M36

Abstract: D0-35 IS61QDB24M18
Contextual Info: 72 Mb 2M x 36 & 4M x 18 QUAD (Burst of 2) Synchronous SRAMs . A May 2009 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations. • Two echo clocks (CQ and CQ) that are delivered

K7D803671B-HC33

Abstract: K7D803671B-HC30 K7D801871B-HC35 K7D801871B-HC37 K7D803671B K7D803671B-HC25 K7D803671B-HC35 K7D803671B-HC37
Contextual Info: K7D803671B K7D801871B 256Kx36 & 512Kx18 SRAM Document Title 8M DDR SYNCHRONOUS SRAM Revision History Rev No. History Draft Data Remark Rev. 0.0 -Initial document. July. 2000 Advance Rev. 0.1 -ZQ tolerance changed from 10% to 15% Aug. 2000 Advance Rev. 0.2

external LCD tv tuner Diagram

Abstract: tvp5147
Contextual Info: TVP5147PFP NTSC/PAL/SECAM 2y10ĆBit Digital Video Decoder With MacrovisionE Detection, YPbPr Inputs, and 5ĆLine Comb Filter Data Manual March 2007 Digital Audio Video SLES099C IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications,

sdc 7500 pwm control

Abstract: sdc 7500 MPC5634M MPC5634 mpc5554 emios bosch Knock sensor MPC5554 instruction set npc 1337 LQFP-144 footprint MPC563
Contextual Info: Freescale Semiconductor Data Sheet: Advance Information Document Number: MPC5634M Rev. 2, 12/2008 MPC5634M MPC5634M Microcontroller Data Sheet • Operating Parameters – Fully static operation, 0 MHz - 80 MHz plus 2% frequency modulation - 82 MHz – -40 °C to 150 °C junction temperature operating range

TSF 1303

Abstract: MAC-07
Contextual Info: EtherMap -3 Device Ethernet into STS-3/STM-1 SONET/SDH Mapper TXC-04226 DATA SHEET PRODUCT PREVIEW TELECOM BUS SIDE +1.8V +3.3V HO/LO RING Ports APPLICATIONS • • • • • HO/LO POH Ports SONET/SDH add/drop and terminal multiplexers Multi-service access platforms

SPC5676

Abstract: TMS 3617 e200z npn transistor RCA 467 MPC567 MPC5676R N3305 PPC5676R GPIO456 UP-K26
Contextual Info: Freescale Semiconductor Data Sheet: Advance Information Document Number: MPC5676R Rev. 3, 9/2012 MPC5676R MPC5676R Microcontroller Data Sheet On-chip modules available within the family include the following features: • Two identical dual issue, 32-bit CPU core complexes

Contextual Info: BurrĆBrown Products from Texas Instruments SR C4 382 SRC4382 SBFS030C – JANUARY 2006 – REVISED SEPTEMBER 2007 Two-Channel, Asynchronous Sample Rate Converter with Integrated Digital Audio Interface Receiver and Transmitter FEATURES 1 • Two-Channel Asynchronous Sample Rate

MPC5668G

Abstract: MPC5668x SPC5668 emios MPC5668 eMIOS200
Contextual Info: Document Number: MPC5668X Rev. 3, 9/2009 MPC5668x MPC5668x Microcontroller Data Sheet MPC5668x features: • 32-bit CPU core complex e200z650 – Compliant with Power Architecture embedded category – 32 KB unified cache with line locking and eight-entry

nrzi Decoder

Abstract: DS32EL0124 DS32EL0124SQ DS32EL0124SQE DS32EL0124SQX DS32ELX0124 DS32ELX0124SQ
Contextual Info: DS32EL0124, DS32ELX0124 125 MHz - 312.5 MHz FPGA-Link Deserializer with DDR LVDS Parallel Interface General Description Features The DS32EL0124/DS32ELX0124 integrates clock and data recovery modules for high-speed serial communication over FR-4 printed circuit board backplanes, balanced cables, and

SSOP-8 PACKAGE

Abstract: PVSP0008KA-A RNA50C27AUS making code DRY
Contextual Info: RNA50C27AUS CMOS System-Reset IC REJ03D0834-0100 Preliminary Rev.1.00 Apr 10, 2006 Description This IC facilitates complicated power-on and power-monitoring resets of microcomputers that require the 3.3-V and 1.8-V dual power supplies. It also facilitates change of delay time of reset signal by externally setting resistance and

DS32ELX0124SQE

Abstract: DS32EL0124 dvi-d 24 pin diagram DS32EL0124SQ DS32EL0124SQE DS32EL0124SQX DS32ELX0124 DS32ELX0124SQ
Contextual Info: DS32EL0124, DS32ELX0124 125 MHz — 312.5 MHz FPGA-Link Deserializer with DDR LVDS Parallel Interface General Description Features The DS32EL0124/DS32ELX0124 integrates clock and data recovery modules for high-speed serial communication over FR-4 printed circuit board backplanes, balanced cables, and

DVD RW sata circuit diagram

Abstract: sata hot plug CIRCUIT diagram REG138
Contextual Info: XRS10L620 PCI-X to 2-SATA/1-PATA Host Controller PRELIMINARY DATA SHEET XRS10L620 Rev 0.11 Index 1. XRS10L620 REVISION HISTORY. 2 2. OVERVIEW . 2

user manual of XRT91L31

Contextual Info: XRT86SH328 SONET TO 28-T1/21-E1 PDH MAPPER - VOYAGER PIN AND ARCHITECTURE DESC MAY 2008 REV. 1.0.0 GENERAL DESCRIPTION The XRT86SH328 Voyager is a physical layer SONET/SDH to PDH mapper/demapper which enables T1/E1 aggregation to STS-3/STM-1 or STS1/ STM0 via standard VT1.5/VT2 or VC-11/VC-12 to

CXK77L18R160GB-3

Abstract: CXK77L18R160GB-33 CXK77L18R160GB-4
Contextual Info: SONY CXK77L18R160GB 16Mb LW R-R HSTL High Speed Synchronous SRAM 1M x 18 3/33/4 Preliminary Description The CXK77L18R160GB is a high speed CMOS synchronous static RAM with common I/O pins, organized as 1,048,576 words by 18 bits. This synchronous SRAM integrates input registers, high speed RAM, output registers, and a one-deep write buffer

Contextual Info: Preliminary Datasheet RNA50C27AUS R03DS0065EJ0200 Rev.2.00 Jul 03, 2012 CMOS System-Reset IC Description This IC facilitates complicated power-on and power-monitoring resets of microcomputers that require the 3.3-V and 1.8-V dual power supplies. It also facilitates change of delay time of reset signal by externally setting resistance and

CXK79M36C163GB

Abstract: CXK79M36C163GB-33 CXK79M36C163GB-4 CXK79M36C163GB-5
Contextual Info: SONY ΣRAM CXK79M36C163GB 18Mb 1x2Lp LVCMOS High Speed Synchronous SRAMs 512Kb x 36 33/4/5 Preliminary Description The CXK79M36C163GB is a high speed CMOS synchronous static RAM with common I/O pins. It is manufactured in compliance with the JEDEC-standard 209 pin BGA package pinout defined for SigmaRAM™ devices. It integrates input registers,

CXK79M36C160GB

Abstract: CXK79M36C160GB-33 CXK79M36C160GB-4 CXK79M36C160GB-5 CXK79M72C160GB CXK79M72C160GB-33 CXK79M72C160GB-4 CXK79M72C160GB-5
Contextual Info: SONY ΣRAM CXK79M72C160GB / CXK79M36C160GB 18Mb 1x1Lp HSTL High Speed Synchronous SRAMs 256Kb x 72 or 512Kb x 36 33/4/5 Preliminary Description The CXK79M72C160GB (organized as 262,144 words by 72 bits) and the CXK79M36C160GB (organized as 524,288 words

CXK79M72C164GB-33

Abstract: CXK79M18C164GB CXK79M36C164GB CXK79M36C164GB-33 CXK79M36C164GB-4 CXK79M72C164GB CXK79M72C164GB-4 CXK79M72C164GB-5
Contextual Info: SONY ΣRAM CXK79M72C164GB CXK79M36C164GB CXK79M18C164GB 18Mb 1x1Dp HSTL High Speed Synchronous SRAMs 256Kb x 72 or 512Kb x 36 or 1Mb x 18 33/4/5 Preliminary Description The CXK79M72C164GB (organized as 262,144 words by 72 bits), CXK79M36C164GB (organized as 524,288 words by 36

Contextual Info: IS61DDP2B22M18A IS61DDP2B21M36A 2Mx18, 1Mx36 36Mb DDR-IIP Burst 2 CIO Synchronous SRAM (2.0 Cycle Read Latency) FEATURES •                   1Mx36 and 2Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid

Contextual Info: IS61QDP2B41M18A IS61QDP2B451236A 1Mx18 , 512Kx36 18Mb QUAD-P Burst 4 SYNCHRONOUS SRAM (2.0 Cycle Read Latency) FEATURES •                    512Kx36 and 1Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid

Contextual Info: IS61QDB41M18A IS61QDB451236A 1Mx18, 512Kx36 18Mb QUAD Burst 4 SYNCHRONOUS SRAM FEATURES •                   512Kx36 and 1Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid