ICS54 Search Results

Contextual Info: ICS542 Clock Divider PRELIMINARY INFORMATION A A icro C lock Description Features The ICS542 is a cost effective way to produce a high quality clock output divided from a clock input. The chip accepts a clock input up to 90 M Hz at 5.0V, and produces a divide by 2, 4, 6,

ICS501

Abstract: ICS541 ICS542 ICS543
Contextual Info: DATASHEET ICS542 CLOCK DIVIDER Description Features The ICS542 is cost effective way to produce a high-quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz at 3.3 V and produces a divide by 2, 4, 6, 8, 12, or 16 of the input clock. There are two outputs

x16 3 marking -ddr -sdram -rimm -sram -flash -m

Abstract: ICS548G-05 ICS548G-05T MK2049-34
Contextual Info: DATASHEET ICS548-05 T1/E1 CLOCK MULTIPLIER Description Features The ICS548-05 is a low-cost, low-jitter, high-performace clock synthesizer designed to produce x16 and x24 clocks from T1 and E1 frequencies. Using ICS’ patented analog/digital PhaseLocked Loop PLL techniques, the device uses a

ICS548-05C

Abstract: ICS548G-05 ICS548G-05T MK2049-34 CRYSTAL 2.048 MHz
Contextual Info: ICS548-05C T1/E1 Clock Multiplier Description Features The ICS548-05C is a low-cost, low-jitter, high-performace clock synthesizer designed to produce x16 and x24 clocks from T1 and E1 frequencies. Using ICS’ patented analog/digital PhaseLocked Loop PLL techniques, the device uses a

ICS542

Abstract: ICS542MLF ICS501 ICS541 ICS542M ICS542MLFT ICS542MT ICS543 542MILF Clock Divider
Contextual Info: DATASHEET ICS542 CLOCK DIVIDER Description Features The ICS542 is cost effective way to produce a high-quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz at 3.3 V and produces a divide by 2, 4, 6, 8, 12, or 16 of the input clock. There are two outputs

Contextual Info: ICS548-03 LOW SKEW CLOCK INVERTER AND DIVIDER Description Features The ICS548-03 is a low cost, low skew, high-performance general purpose clock designed to produce a set of one output clock, one inverted output clock, and one clock divided-by-two. Using our

Contextual Info: ICS543 Clock Divider and 2X Multiplier Description Features The ICS543 is cost effective way to produce a high quality clock output divided from a clock input. The chip accepts a clock input up to 90 MHz at 5.0 V. Using proprietary Phase Locked-Loop PLL techniques, the

Contextual Info: PRELIMINARY INFORMATION ICROCLOCK ICS542 Clock Divider Description Features The ICS542 is a cost effective way to produce a high quality clock output divided from a clock input. The chip accepts a clock input up to 90 MHz at 5.0V, and produces a divide by 2, 4, 6,

ICS548-03

Abstract: ICS548M-03 ICS548M-03T ICS570 S3S2
Contextual Info: ADVANCE INFORMATION ICS548-03 Low Skew Clock Inverter and Divider Description Features The ICS548-03 is a low cost, low skew, high performance general-purpose clock designed to produce a set of one output clock, one inverted output clock, and one clock divided-by-2. Using

ICS548-05C

Abstract: ICS548G-05 ICS548G-05T MK2049-34
Contextual Info: PRELIMINARY INFORMATION ICS548-05C T1/E1 Clock Multiplier Description Features The ICS548-05C is a low cost, low jitter, high performance clock synthesizer designed to produce x16 or x24 clocks from T1 or E1 frequencies. Using ICS’ patented analog/digital

ICS542MLF

Abstract: ICS542MLFT ICS501 ICS541 ICS542 ICS542M ICS542MT ICS543
Contextual Info: ICS542 Clock Divider Description Features The ICS542 is cost effective way to produce a high-quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz at 3.3 V and produces a divide by 2, 4, 6, 8, 12, or 16 of the input

ICS501

Abstract: ICS541 ICS542 ICS542M ICS542MLF ICS542MLFT ICS542MT ICS543
Contextual Info: ICS542 Clock Divider Description Features The ICS542 is cost effective way to produce a high-quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz at 3.3 V. Using proprietary Phase-Locked Loop PLL techniques, the device produces a divide by 2, 4, 6, 8,

3.6864

Abstract: ICS548-05A ICS548G-05 ICS548G-05T
Contextual Info: PRELIMINARY INFORMATION ICS548-05A MP3 Audio Clock Description Features The ICS548-05 is a low cost, low jitter, high performance clock synthesizer designed to produce audio sampling rates for MP3 systems. Using ICS’ patented analog/digital Phase-Locked

ICS501

Abstract: ICS541 ICS542 ICS542M ICS542MT ICS543
Contextual Info: ICS542 Clock Divider Description Features The ICS542 is cost effective way to produce a high quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz at 3.3V. Using proprietary Phase Locked-Loop PLL techniques, the device produces a divide by 2, 4, 6, 8, 12, or 16 of the

Contextual Info: ICS548-03 LOW SKEW CLOCK INVERTER AND DIVIDER Description Features The ICS548-03 is a low cost, low skew, high-performance general purpose clock designed to produce a set of one output clock, one inverted output clock, and one clock divided-by-two. Using our

ICS542

Contextual Info: DATA SHEET ICS542 ICS542 Clock Divider Clock Divider Description Features The ICS542 is cost effective way to produce a high-quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz at 3.3 V and produces a divide by 2, 4, 6, 8, 12, or 16 of the input

ICS548-05

Contextual Info: DATA SHEET ICS548-05 ICS548-05 T1/E1 Clock Multiplier T1/E1 Clock Multiplier Description Features The ICS548-05 is a low-cost, low-jitter, high-performace clock synthesizer designed to produce x16 and x24 clocks from T1 and E1 frequencies. Using ICS’ patented analog/digital PhaseLocked Loop PLL techniques, the device uses a

ICS542MILF

Contextual Info: DATASHEET ICS542 CLOCK DIVIDER Description Features The ICS542 is cost effective way to produce a high-quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz at 3.3 V and produces a divide by 2, 4, 6, 8, 12, or 16 of the input clock. There are two outputs

Contextual Info: DATASHEET T1/E1 CLOCK MULTIPLIER I CS5 4 8 -0 5 Description Features The ICS548-05 is a low-cost, low-jitter, high-performace clock synthesizer designed to produce x16 and x24 clocks from T1 and E1 frequencies. Using IDT’s patented analog/digital Phase- Locked Loop PLL techniques, the device uses

TAG 8434

Abstract: transistor tag 8422 ICODE SLI-S MOA2 ICS53 ICS5401 ICODE SLI Icode antenna design SL2FCS5301EV
Contextual Info: SL2 ICS53/SL2 ICS54 I•CODE SLI-S/I•CODE SLI-S HC Rev. 3.0 — 14 March 2007 113730 Product data sheet PUBLIC 1. General description The I•CODE SLI-S/I•CODE SLI-S HC IC is a dedicated chip for smart label applications with the need for a higher security level, larger memory and/or a product which takes care

S-541A

Abstract: S541A
Contextual Info: PRELIMINARY INFORMATION ICS541 PLL Clock Divider Description Features The ICS541 is a cost effective way to produce a high quality clock output divided from a clock input. The chip accepts a clock input up to 90 M Hz at 5.0V, and by using proprietary Phase

ICS501

Abstract: ICS541 ICS542 ICS542M ICS542MT ICS543
Contextual Info: ICS542 Clock Divider Description Features The ICS542 is a cost effective way to produce a high quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz, and produces a divide by 2, 4, 6, 8, 12, or 16 of the input clock. There are two outputs on

4020 divider

Abstract: ICS300 ICS541 ICS541M ICS541MT ICS542 ICS543
Contextual Info: PRELIMINARY INFORMATION ICS541 PLL Clock Divider Description Features The ICS541 is a cost effective way to produce a high quality clock output divided from a clock input. The chip accepts a clock input up to 135 MHz at 3.3 V, and by using proprietary Phase

ICS548A-03

Abstract: ICS548AM-03LF ICS548AM-03LFT ICS548AMI-03LF ICS570 inverter techniques
Contextual Info: DATASHEET ICS548A-03 LOW SKEW CLOCK INVERTER AND DIVIDER Description Features The ICS548A-03 is a low cost, low skew, high-performance general purpose clock designed to produce a set of one output clock, one inverted output clock, and one clock divided-by-two. Using our patented Phase-Locked Loop