ICO 143 Search Results

LG 631 IC

Abstract: SDXC pin diagram of tle 7203 F804 F808 HSP50216 HSP50216KI tle 8209 e SD2C tle 8209
Contextual Info: HSP50216 TM Data Sheet tle P5 6 jec rnn ra abl ital n ver tho w rsi por n, ico cto Four-Channel Programmable Digital DownConverter The HSP50216 Quad Programmable Digital DownConverter QPDC) is designed for high dynamic range applications such as cellular basestations where multiple channel processing is

TIM6472-4SL

Abstract: to 92 case
Contextual Info: TOSHIBA MICROWAVE POWER GaAs FET M ICROW AVE SEM ICO NDU CTO R TIM6472-4SL TECHNICAL DATA FEATURES : • LOW INTERMODULATION DISTORTION ■ HIGH EFFICIENCY qadd = 34 % at 6.4 GHz to 7.2 GHz IM 3 = - 4 5 dBc at Po = 25.5 dBm, Single Carrier Level ■ ■ HIGH GAIN

Contextual Info: TOSHIBA MICROWAVE POWER GaAs FET M ICROW AVE SEM ICO NDU CTO R TIM6472-14L TECHNICAL DATA FEATURES : • LOW INTERMODULATION DISTORTION HIGH GAIN IM3 = - 4 5 dBc at Po = 31.5 dBm, G’jdQ = 7.5 dB at 6.4 GHz to 7.2 GHz Single Carrier Level ■ BROAD BAND INTERNALLY MATCHED

Contextual Info: ALUMINUM ELECTROLYTIC CAPACITORS n ich ico n Compact & Low-Profile Sized, Wide Temperature Range 3 B series Srraler Arrii-Solvsnl Feaijre Til rough 100V only} • Very sm all case sizes same as RS series, but operating over wide tem perature range of — 55 ( —40} •— H 0 5 'C .

Contextual Info: FUJITSU S EM ICO NDUCTO R DATA SHEET ASSP Communication Control Data Link Controller DLC MB89374 • DESCRIPTION The MB89374 Data Link Controller (DLC) controls transfer of serial data in accordance with Bit Oriented Protocol (BOP). It supports protocols such as High level Data Link Control (HDLC) (the BOP mode) and Serial Data

Contextual Info: T O S H IB A MICROWAVE POWER G aAs FET M ICROW AVE SEM ICO NDU CTO R TPM1818-30 TECHNICAL DATA FEATURES: • HIGH POWER ■ HIGH GAIN ■ PARTIALLY MATCHED TYPE ■ HERMETICALLY SEALED PACKAGE pidB = 44.5 dBm at 1.8 GHz G-idB = ^2 dB at 1.8 GHz RF PERFORMANCE SPECIFICATIONS Ta = 25°C

Contextual Info: Ä PLESSE Y W S e m ico n d u cto rs. SP8794AC 60MHz -r 8 TWO MODULUS EXTENDER CONFORMS TO MIL-STD-883C CLASS B The SP8790 is a divide-by-eight counter designed fo r use with 2-m odulus counters. It increases the m inim um division ratio of the 2-m odulus counter while retaining the same

SKE33

Abstract: SKE68A SKE400A ske36 1.SKE180 SKE400
Contextual Info: GENERAL SEMICONDUCTOR 3918590 G EN ERAL TS SEM ICO N D U C TO R Ï F| B IIÛ ST O 95D 01983 0 D Q n û 3 / / -J 3 General ^ Semiconductor ^ Industries, Inc. Tr a n s Zo r b ® ^ FEATU RES 1500 watts Peak Pulse Power dissipation Fast Response Available In ranges from 6.8 to 400

PM5312

Abstract: PM5344 PM5345 lcsb P8095 paei pm5312 pmc-sierra
Contextual Info: PM5312 STTX DATA SHEET ISSUE 5 SONET/SDH TRANSPORT TERMINATING TRANSCEIVER :5 1: 25 AM PMC-930829 ve m be r, 20 02 09 PM5312 y, 19 No STTX er to n Tu es da SONET/SDH TRANSPORT OVERHEAD TERMINATING TRANSCEIVER TELECOM STANDARD PRODUCT ISSUE 5: JULY 1998 Do

w1869

Abstract: S-1768
Contextual Info: REVISIONS L TR DESCRIPTION SEE PACKAGE XI D E S I GNATOR A B C D E F G H J K L M N P R S T U V XI PACKAGE WI DTH ±30/£m 1006 1031 1057 1082 1107 1 133 1 1 58 1184 1209 1234 1260 1285 1311 1336 1361 1387 1412 1438 1463 1488 X2 D E S I GNATOR A B C D E F G

MO-211

Contextual Info: REVISIONS L TR DESCRIPTION SEE PACKAGE XI D E S IGNATOR A B C D E F G H J K L M N P R S T U XI PACKAGE WIDTH i3 0 /£ m 1006 1031 1057 1082 1107 1 133 1 1 58 1184 1209 1234 1260 1285 1311 1336 1361 1387 1412 1438 1463 X2 D E S IGNATOR A B C D E F G H J K L

LG color tv Circuit Diagram schematics

Abstract: MD 1803 FX MN102L35G 27C202 eprom 711S SERVICE MANUAL Panasonic Panasonic color television schematic diagram ls010 lg led tv internal parts block diagram LG 631 TV LG
Contextual Info: P a n iB r i n g i n g a X S ‘l o m o T r o z v MICROCOMPUTER MN102L35G LSI User Manual Ver. 2.20 March 6, 1998 Panasonic • ^ 3 2 6 5 2 0016705 273 ■ This Material Copyrighted By Its Respective Manufacturer e rie s t o ‘T o d a y Restrictions and Warnings Regarding the Use of the Technical Data and the

Nippon capacitors

Contextual Info: HB56U272E Series 2,097,152-word x 72-bit High Density Dynamic RAM Module HITACHI ADE-203-713A Z Rev. 1.0 Jan. 27, 1997 Description The HB56U272E belongs to 8 Byte DIMM (Dual In-line Memory Module) family, and has been developed as an optimized main memory solution for 4 and 8 Byte processor applications. The HB56U272E is a 2M

Contextual Info: HB56A164EJ Series 1,048,576-word x 64-bit High Density Dynamic RAM Module HITACHI ADE-203Rev. 0.0 Dec. 1, 1995 Description The HB56A164EJ belongs to 8 byte DIMM Dual In-line Memory Module family, and has been developed as an optimized main memory solution for 4 and 8 Byte processor applications.

Contextual Info: . _ n « PRELIMINARY Ultra37032V UltraLogic 32-Macrocell ISR™ CPLD — tPD = 8.5 ns Features — ts = 5.0 ns • 32 macrocells in two logic blocks • 3.3V In-System Reprogrammable™ ISR™ — tco = 6.0 ns • • • • • • — JTAG-compliant on-board programming

palce16v8-25pi

Contextual Info: fax id: 6009 PALCE16V8 «f c y p r e s s Flash Erasable, Reprogrammable CMOS PAL Device • QSOP packaging available Features — 7.5 ns com ’l version 5 ns tCo 5 ns ts 7.5 ns tPD 125-MHz state machine • Active pull-up on data input pins • Low power version 16V8L

ne555 vco

Abstract: NE555CN NE555C NE555CD IC NE555c ne556 application NE555 NE556 samsung timer ne555
Contextual Info: SAMSUNG ELEC TRONICS INC 4 HE 5 711*4142 □□0=143=] 0 HUSflGK LINEAR INTEGRATED CIRCUIT NE555C SINGLE TIMER The NE555 is a highly stable controller capable of producing accurate timing pulses. With monostable operation, the time delay Is controlled by one external and one capacitor. With astable operation,

39S256160T

Abstract: PC100-333-620 IT191 s4 marking code siemens SMD MARKING CODE A12 smd marking KH P-TSOPII-54
Contextual Info: H Y B 39S 25 640 0/8 00/1 60 T 256M B it S ynch ro n o u s DRAM S IE M E N S 2 5 6 M B it S y n c h ro n o u s D R A M P re lim in a ry In fo rm a tio n • High Perform ance: Multiple Burst Operation -8 -8B -10 Units fC K 125 100 100 M Hz tC K 3 8 10 10 ns

Contextual Info: SAMSUNG S E M I C O ND U CT OR INC D2 ' ' ¡>Ëj 7 ^ 4 1 4 2 ' KS5112 OOOSbSl 0 §1 5651 D ^ ° *CMOS DIGITAL INTEGRATED CIRCUIT 5-FUNCTION 6-DIGIT WATCH CIRCUIT FOR TRIPLEXED LCD. The KS5112 is a CMOS LSI which contains all logic necessary to implement a five function, six digits liquid crystal display watch. The

Contextual Info: STI641004G1-60VG 144-PIN SO-DIMMS 1M X 64 Bits DRAM SO-DIMM Memory Module FEATURES GENERAL DESCRIPTION • The Simple Technology STI641004G1-60VG is a 1M x 64 bits Dynamic RAM high density memory module. The Simple Technology STI641004G1-60VG consist of four CMOS 1M x

PALCE22V10D

Abstract: PALGE22 PALCE22 palce22v10 programming guide
Contextual Info: P A L C E 2 2 V1 0 Flash Erasable, Reprogrammable CMOS Pal Device 5 ns tpD 181 -MHz state m achine Features * Low pow er — 10 ns m ilita ry and in d u s tria l v e rs io n s 7 ns tco 6 ns ts 10 ns tp D 11 0-MHz state m achine — 90 mA max. com m ercia l 10 ns

8 ohm 0.25w SPEAKER

Abstract: cuckoo clock cuckoo MSS0306 TG16 TG17 TG32 8 ohm 0.25w buzzer 5100H
Contextual Info: MOSEL VITELIC MSS0306 3" VOICE ROM Features Single power supply can operate at 2.4V through 4.5V. Current output can drive 8 ohm speaker with a transistor. The voice content is stored up to 3.5 seconds 5100h and can be separated to 8 sections. Five trigger input pins are provided. Each trigger

Contextual Info: fax id: 6148 CYPRESS PRELIMINARY Ultra37256 UltraLogic 256-Macrocell ISR™ CPLD Features — ts = 4.5 ns — tco = 5.0 ns • 256 macrocells in sixteen logic blocks • In-System Reprogram mable ISR™ Product-term clocking IEEE1149.1 JTAG boundary scan

Contextual Info: ,!!!!!!ifSmfím ^ . „ n « Ultra37384V PRELIMINARY UltraLogic 3.3V 384-Macrocell ISR™ CPLD Features — tPD = 15 ns — ts = 8 ns • 384 macrocells in 24 logic blocks • 3.3V In-System Reprogrammable™ ISR™ — tco = 8 ns • • • • •