ICE40LP384SG32 Search Results
ICE40LP384SG32 Datasheets (3)
| Part | ECAD Model | Manufacturer | Description | Datasheet Type | PDF Size | Page count | |
|---|---|---|---|---|---|---|---|
| ICE40LP384-SG32 |
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Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 21 I/O 32QFN | Original | 43 | |||
| ICE40LP384-SG32TR |
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Integrated Circuits (ICs) - Embedded - FPGAs (Field Programmable Gate Array) - IC FPGA 21 I/O 32QFN | Original | 3.31MB | |||
| ICE40LP384-SG32TR1K |
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Integrated Circuits (ICs) - Embedded - FPGAs (Field Programmable Gate Array) - IC FPGA 21 I/O 32QFN | Original | 3.31MB |
ICE40LP384SG32 Price and Stock
Lattice Semiconductor Corporation ICE40LP384-SG32IC FPGA 21 I/O 32QFN |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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ICE40LP384-SG32 | Tray | 1,508 | 1 |
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ICE40LP384-SG32 | 3,822 |
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ICE40LP384-SG32 | 12,755 | 4 |
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ICE40LP384-SG32 | 12,755 | 24 Weeks | 1 |
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ICE40LP384-SG32 | Bulk | 1,317 | 1 |
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ICE40LP384-SG32 | 43,652 |
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ICE40LP384-SG32 | 27,257 |
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ICE40LP384-SG32 | 14,350 |
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Lattice Semiconductor Corporation ICE40LP384-SG32TRIC FPGA 21 I/O 32QFN |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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ICE40LP384-SG32TR | Tape & Reel | 20,000 |
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ICE40LP384-SG32TR |
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ICE40LP384-SG32TR | Tape & Reel | 20,000 |
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ICE40LP384-SG32TR | 988 |
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Lattice Semiconductor Corporation ICE40LP384-SG32TR1KIC FPGA 21 I/O 32QFN |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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ICE40LP384-SG32TR1K | Tape & Reel | 10,000 |
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ICE40LP384-SG32TR1K |
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ICE40LP384-SG32TR1K | Tape & Reel | 10,000 |
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ICE40LP384-SG32TR1K | 551 |
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ICE40LP384-SG32TR1K | 52,000 |
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Get Quote | |||||||
ICE40LP384SG32 Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
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Contextual Info: iCE40 LP/HX Family Data Sheet DS1040 Version 02.9, April 2014 iCE40 LP/HX Family Data Sheet Introduction February 2014 Data Sheet DS1040 Features Flexible Logic Architecture – Schmitt trigger inputs, to 200 mV typical hysteresis • Programmable pull-up mode |
Original |
iCE40â DS1040 iCE40 DS1040 LP384 | |
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Contextual Info: iCE40 LP/HX Family Data Sheet DS1040 Version 02.5, August 2013 iCE40 LP/HX Family Data Sheet Introduction August 2013 Data Sheet DS1040 Flexible On-Chip Clocking Features • Eight low-skew global clock resources • Up to two analog PLLs per device |
Original |
iCE40â DS1040 iCE40 DS1040 Distribut2013 | |
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Contextual Info: iCE40 LP/HX Family Data Sheet DS1040 Version 02.4, July 2013 iCE40 LP/HX Family Data Sheet Introduction July 2013 Data Sheet DS1040 Flexible On-Chip Clocking Features • Eight low-skew global clock resources • Up to two analog PLLs per device Flexible Logic Architecture |
Original |
iCE40â DS1040 iCE40 DS1040 | |
LATTICE SEMICONDUCTOR Tape and Reel Specification
Abstract: LVDS25E 0.4mm pitch BGA routing ICE40 FPGA pitch 0.4mm BGA 0.4mm pitch 2.5x2.5mm
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Original |
iCE40TM DS1040 iCE40 DS1040 LATTICE SEMICONDUCTOR Tape and Reel Specification LVDS25E 0.4mm pitch BGA routing ICE40 FPGA pitch 0.4mm BGA 0.4mm pitch 2.5x2.5mm | |
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Contextual Info: iCE40 LP/HX Family Data Sheet DS1040 Version 02.6, September 2013 iCE40 LP/HX Family Data Sheet Introduction August 2013 Data Sheet DS1040 Flexible On-Chip Clocking Features • Eight low-skew global clock resources • Up to two analog PLLs per device |
Original |
iCE40â DS1040 iCE40 DS1040 | |
ICE40 lattice
Abstract: ICE40 FPGA 0.4mm pitch BGA routing TN1251 ICE40LP1K ICE40LP1K-CM36 GDDR71 pitch 0.4mm BGA 0.4mm pitch 2.5x2.5mm ICE40LP384SG32
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iCE40TM DS1040 iCE40 DS1040 ICE40 lattice ICE40 FPGA 0.4mm pitch BGA routing TN1251 ICE40LP1K ICE40LP1K-CM36 GDDR71 pitch 0.4mm BGA 0.4mm pitch 2.5x2.5mm ICE40LP384SG32 | |
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Contextual Info: iCE40 LP/HX Family Data Sheet DS1040 Version 02.7, October 2013 iCE40 LP/HX Family Data Sheet Introduction October 2013 Data Sheet DS1040 Flexible On-Chip Clocking Features • Eight low-skew global clock resources • Up to two analog PLLs per device |
Original |
iCE40â DS1040 iCE40 DS1040 iCE40-1K iCE40LP/HX1K iCE40LP640 | |
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Contextual Info: iCE40 LP/HX Family Data Sheet DS1040 Version 3.0, July 2014 iCE40 LP/HX Family Data Sheet Introduction February 2014 Data Sheet DS1040 Features Flexible Logic Architecture – Schmitt trigger inputs, to 200 mV typical hysteresis • Programmable pull-up mode |
Original |
iCE40â DS1040 iCE40 DS1040 iCE40LP1K. | |
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Contextual Info: iCE40 LP/HX/LM Family Handbook HB1011 Version 01.2, November 2013 iCE40 LP/HX/LM Family Handbook Table of Contents October 2013 Section I. iCE40 LP/HX Family Data Sheet Introduction Features . 1-1 |
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iCE40â HB1011 iCE40 TN1251 | |
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Contextual Info: iCE40 LP/HX Family Data Sheet DS1040 Version 02.8, February 2014 iCE40 LP/HX Family Data Sheet Introduction February 2014 Data Sheet DS1040 Features – Schmitt trigger inputs, to 200 mV typical hysteresis • Programmable pull-up mode Flexible Logic Architecture |
Original |
iCE40â DS1040 iCE40 DS1040 iCE40-1K iCE40LP/HX1K iCE40LP640 iCE40LP1K |