ICC100 Search Results

ICC1-100

Abstract: ICC150
Contextual Info: REVISIONS LTR DESCRIPTION DATE YR-MO-DA APPROVED A Add device type 02. Inactivate device type 01 (no approved source of supply). Add device types 03 through 07. Add vendors CAGE 32116, 5Y243, 57363, and 88379. Changed to reflect MIL-H-38534 processing. Editorial changes throughout.

NHI-1582ETGW

Abstract: NHI-1582ETGW/883 GAP01 super avr manual ET 8211 NHI-1582ET stanag 4444 STD-1553A A5690 mil bus
Contextual Info: NATIONAL HYBRID, Inc. Multi Protocol Data Bus Interface NHi-ET Enhanced Terminals Bus Controller, Remote Terminal, Bus Monitor User's Manual Version 2000.11.29 November 2000 The information provided in this document is believed to be accurate; however, no responsibility is assumed by NATIONAL

CDCLVD2104RHDR

Contextual Info: CDCLVD2104 www.ti.com SCAS903A – JUNE 2010 – REVISED AUGUST 2010 Dual 1:4 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD2104 FEATURES 1 • • • • • • • • • • • • Dual 1:4 Differential Buffer Low Additive Jitter <300 fs, RMS in

4092B

Abstract: LA1861 LA1861M mitsumi COIL mitsumi modulator LA1862M stereo audio to mitsumi modulator mitsumi modulator enc-87941 mitsumi am fm tuner mitsumi f23
Contextual Info: Ordering number: EN 4092B Monolithic Linear IC LA1862M Single-chip Tuner System for Car Stereo Overview Package Dimensions The LA1862M is a single-chip car stereo FM IF/NC/MPX tuner IC which offers improved IF stability and S-meter characteristics, compared with the LA1861M.

CT3231M

Abstract: HD-15530 technitrol t1553
Contextual Info: Standard Products CT3231M Low Power Driver / Receiver for MIL-STD-1553B & SAE-AS15531 www.aeroflex.com/Avionics March 15, 2005 FEATURES ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ ±12V to ±15V/+5V DC power supply operation 1.5Watt total hybrid dissipation at 25% transmitting duty cycle

Contextual Info: CDCLVD2108 www.ti.com SCAS905C – OCTOBER 2010 – REVISED DECEMBER 2010 Dual 1:8 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD2108 FEATURES 1 • • • • • • • • • • • • Dual 1:8 Differential Buffer Low Additive Jitter <300 fs RMS in

Contextual Info: CDCLVD2104 www.ti.com SCAS903A – JUNE 2010 – REVISED AUGUST 2010 Dual 1:4 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD2104 FEATURES 1 • • • • • • • • • • • • Dual 1:4 Differential Buffer Low Additive Jitter <300 fs, RMS in

CDCLVD1204

Contextual Info: CDCLVD1204 www.ti.com SCAS898A – MAY 2010 – REVISED JUNE 2010 2:4 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD1204 FEATURES DESCRIPTION • • The CDCLVD1204 clock buffer distributes one of two selectable clock inputs, IN0, IN1 , to 4 pairs of

Contextual Info: CDCLVD2108 www.ti.com SCAS905C – OCTOBER 2010 – REVISED DECEMBER 2010 Dual 1:8 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD2108 FEATURES 1 • • • • • • • • • • • • Dual 1:8 Differential Buffer Low Additive Jitter <300 fs RMS in

Contextual Info: CDCLVD1212 www.ti.com SCAS901B – SEPTEMBER 2010 – REVISED JANUARY 2011 2:12 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD1212 FEATURES 1 • • • • • • • • • • • • 2:12 Differential Buffer Low Additive Jitter: <300 fs RMS in

NHI-156XX

Abstract: TAG 9031 15XXX NHI-15XX 56xx stanag 4007
Contextual Info: NATIONAL HYBRID, Inc. NHi-156XX Terminals NHi-157XX Terminals Bus Controller, Remote Terminal, Bus Monitor PCI Bus And Local Bus Host Interface User's Manual Version 2007.02.24 February 2007 The information provided in this document is believed to be accurate; however, no responsibility is assumed by NATIONAL

NHI-1517

Abstract: NHI-1513 NHI-1514
Contextual Info: NATIONAL HYBRID, INC. = NHî 2200 Smithtown Avenue, Ronkonkoma, NY 11779 516 981-2400 FAX 516-981-244S Sales FAX 616-981-8888 Mil-Std-1772 Certified & Qualified Mil-Std-1553/MacAir Products NHI-1513 Series Voltage Driver Single Transceivers FEATURES: 1.5 W att Total Hybrid D issipation at 25% Transm itting

d2102

Contextual Info: CDCLVD2102 www.ti.com SCAS904A – MAY 2010 – REVISED JUNE 2010 Dual 1:2 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD2102 FEATURES 1 • • • • • • • • • • • • Dual 1:2 Differential Buffer Low Additive Jitter <300 fs RMS in 10-kHz to

5962-8959201XX

Abstract: ARX3404 22202 QML-38534 ARX3407 MIL-STD-481 Instructions ARX3407-001FP ARX3404FP
Contextual Info: NOTICE OF REVISION NOR (See MIL-STD-480 for instructions) This revision described below has been authorized for the document listed. DATE (YYMMDD) Form Approved OMB No. 0704-0188 91-11-06 Public reporting burden for this collection is estimated to average 1 hour per response, including the time for reviewing instructions, searching

BUS-63105

Abstract: 5962-8604902ZX ARX2402 ARX3402 22202 BUS-63105II qml-38534 CT1487M NHI 1509 63105
Contextual Info: 1. DATE YYMMDD NOTICE OF REVISION (NOR) This revision described below has been authorized for the document listed. 95-07-12 Public reporting burden for this collection is estimated to average 2 hours per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining the data needed, and completing

Contextual Info: CDCLVD1208 www.ti.com SCAS899 – AUGUST 2010 2:8 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD1208 FEATURES 1 • • • • • • • • • • • • 2:8 Differential Buffer Low Additive Jitter: <300 fs RMS in 10 kHz to 20 MHz Low Output Skew of 45 ps Max

CDCLVD1204

Contextual Info: CDCLVD1204 www.ti.com SCAS898A – MAY 2010 – REVISED JUNE 2010 2:4 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD1204 FEATURES DESCRIPTION • • The CDCLVD1204 clock buffer distributes one of two selectable clock inputs, IN0, IN1 , to 4 pairs of

Contextual Info: CDCLVD2108 www.ti.com SCAS905C – OCTOBER 2010 – REVISED DECEMBER 2010 Dual 1:8 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD2108 FEATURES 1 • • • • • • • • • • • • Dual 1:8 Differential Buffer Low Additive Jitter <300 fs RMS in

MLT 22 805

Abstract: intel 82555 25 MHZ TXC 82555 intel 10BASE-T-FDX IEEE 802.3 10BaseT 10BASET 100BASE-TX Intel Express 7135 led driver 625225
Contextual Info: INTEL 82555 10/100 Mbps LAN PHYSICAL LAYER INTERFACE n Optimal integration for lower cost solution  Integrated 10/100 Mbps single chip solution.  MQFP 100 pin package.  Complete 10/100 Mbps Media Independent Interface MII compliance with MDI support.

STE100

Abstract: STE100P TQFP64 nrz to nrzi decoder duplex clock led display
Contextual Info: STE100P 10/100 FAST ETHERNET 3.3V TRANSCEIVER 1.0 DESCRIPTION The STE100P, also referred to as STEPHY1, is a high performance Fast Ethernet physical layer interface for 10Base-T and 100Base-TX applications. It was designed with advanced CMOS technology to

lnk 3060

Contextual Info: STE400P 10/100 FAST ETHERNET 4 PORT TRANSCEIVER 1 GENERAL DESCRIPTION The STE400P, also referred to as STEPHY4, is a high performance Fast Ethernet physical layer interface for 10BASE-T and 100BASE-TX applications. It was designed with advanced CMOS technology to

CT1487M

Abstract: CT1487MFP CT1589M CT1487D
Contextual Info: THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS CT1487M/CT1589M OCTOBER 1991 3122-1.2 CT1487M/CT1589M MIL-STD-1553 LOW POWER SINGLE AND DUAL TRANSCEIVERS FEATURES GENERAL DESCRIPTION • Available in ±15V CT1487M and ±12 V (CT1589M)

40spq

Contextual Info: CDCLVD2106 www.ti.com SCAS902B – SEPTEMBER 2010 – REVISED JANUARY 2011 Dual 1:6 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD2106 FEATURES 1 • • • • • • • • • • • • Dual 1:6 Differential Buffer Low Additive Jitter: <300 fs rms

Contextual Info: CDCLVD1212 www.ti.com SCAS901 – SEPTEMBER 2010 2:12 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD1212 FEATURES 1 • • • • • • • • • • 2:12 Differential Buffer Low Additive Jitter: <300 fs RMS in 10 kHz to 20 MHz Low Output Skew of 50 ps Max