IC 93CS46 Search Results

NET1080

Abstract: 93C56L 93C46L 93CS56 netchip pioneer pll 10BT 93CS06 93CS46 93CS66
Contextual Info: NetChip Technology, Inc. 335 Pioneer Way Mt View, California 94041 650 526-1490 Fax (650) 526-1494 e-mail: sales@netchip.com Internet: www.netchip.com NET1080 USB TurboCONNECT PRELIMINARY SPECIFICATION For Revision 2 IC Doc #: 605-1080-0206 Revision: 0.6

M08A

Abstract: MTC08 NM93CS46
Contextual Info: e m ic o n d u c to r NM93CS46 MICROWIRE™ Bus Interface 1024-Bit Serial EEPROM with Data Protect and Sequential Read General Description Features The NM93CS46 devices are 1024 bits of CMOS non-volatile electrically erasable memory divided into 64 16-bit registers.

Contextual Info: s e m ic o n d u c t o r NM93CS46 MICROWIRE™ Bus Interface 1024-Bit Serial EEPROM with Data Protect and Sequential Read General Description Features The NM93CS46 devices are 1024 bits of CMOS non-volatile electrically erasable memory divided into 64 16-bit registers.

M08A

Abstract: MTC08 NM93CS46
Contextual Info: s e m ic d n d u c t d r t m NM93CS46 MICROWIRE Bus Interface 1K-Bit Serial EEPROM with Data Protect and Sequential Read General Description Features The NM93CS46 devices are 1024 bits of CMOS non-volatile electrically erasable memory divided into 64 16-bit registers.

ac 5v adapter circuit schematic

Abstract: 93CS56 hitachi sh3 74LVT16245 PCI9080 Hitachi SH3 PCI Host Bridge IC 93cs46
Contextual Info: PCI to SH-3 AN Hitachi SH3  to PCI bus Application Note Version 1.0 FEATURES _ GENERAL DESCRIPTION _ • This application note describes how to interface the Hitachi SH-3 CPU to the PCI bus using the PLX PCI 9080 "PCI to Local Bus Bridge" IC in a PCI

M08A

Abstract: MTC08 NM93CS46
Contextual Info: s e m ic d n d u c t d r t m NM93CS46 MICROWIRE Bus Interface 1K-Bit Serial EEPROM with Data Protect and Sequential Read General Description Features The NM93CS46 devices are 1024 bits of CMOS non-volatile electrically erasable memory divided into 64 16-bit registers.

Contextual Info: SEMICONDUCTOR TM NM93CS46 MICROWIRE Bus Interface 1024-Bit Serial EEPROM with Data Protect and Sequential Read General Description Features The NM93CS46 devices are 1024 bits of CMOS non-volatile electrically erasable memory divided into 64 16-bit registers.

Contextual Info: NM93CS46 F A I R C H IL D SEMICONDUCTOR TM NM93CS46 MICROWIRE Bus Interface 1024-Bit Serial EEPROM with Data Protect and Sequential Read General Description Features The NM93CS46 devices are 1024 bits of CMOS non-volatile electrically erasable memory divided into 64 16-bit registers.

USS720

Abstract: 93CS56 Chn 835 93CS46l
Contextual Info: m i c r o e l e c t r o n i c s group Preliminary Data Sheet, Rev. 2 February 1999 Lucent Technologies Bell Labs Innovations f f 0 D « USS-720 Instant USB USB-to-IEEE* 1284 Bridge u n iv e r s a l s e r i a l b u s Features • Supports standard PC parallel port register-based

USS720

Contextual Info: m i c r o e l e c t r o n i c s group Preliminary Data Sheet, Rev. 3 May 1999 Lucent Technologies Bell Labs Innovations f f 0 D « USS-720 Instant USB USB-to-IEEE* 1284 Bridge u n iv e r s a l s e r i a l b u s Features • Supports standard PC parallel port register-based

Contextual Info: PCI 9050 TE August 31, 1996 VERSION 1.0 PCI Bus Target Interface Chip for Low Cost Adapters Featu res_ General Description_ • PCI Specification 2.1 Com pliant Target Interface Chip supporting low cost slave adapters. A llow s simple

P-CDL

Abstract: D0014S3 10B5 38E9 93CS56 NM93CS46 PCI9050
Contextual Info: Æ Q C * . P T e c T H T S -rS -S T X August 31, 1996 VERSIO N 1.0 C 9 I 5 PCI Bus Target Interface Chip for Low Cost Adapters Featu res_ General Description_ • PCI Specification 2.1 Com pliant Target Interface Chip

mxo45 application notes

Abstract: bob smith termination IR10D aui isolation transformer T3D 34 diode BF 195 pin configuration The LXT9883/LXT9863 Data Sheet TRANSISTOR BC 187 LXT9880 t3d 68
Contextual Info: Advanced 10/100 Repeater with Integrated Management — LXT9860/9880 Contents 1.0 Other Related Documents…. 11 2.0 Pin Assignments and Signal Descriptions . 12

IR10D

Abstract: LXT918 LXT980 LXT9860 LXT9880 The LXT98x0 Design and Layout Guide
Contextual Info: LXT9860/9880 Advanced 10/100 Repeater with Integrated Management Datasheet The LXT9880 is the next-generation repeater family, integrated with eight 10/100 transceivers. The LXT9880 is compatible with previous generations of Intel repeaters from the LXT980 and

IR10E

Abstract: IR10D 248987
Contextual Info: LXT9860/9880 Advanced 10/100 Repeater with Integrated Management Datasheet The LXT9880 is the next-generation repeater family, integrated with eight 10/100 transceivers. The LXT9880 is compatible with previous generations of Intel repeaters from the LXT980 and

Ir10e

Abstract: QB 2104 TRANSISTOR IR10D
Contextual Info: Cortina Systems LXT9860/LXT9880 Advanced 10/100 Repeater with Integrated Management Datasheet The Cortina Systems® LXT9860/LXT9880 Advanced 10/100 Repeater with Integrated Management LXT98x0 Repeater is the next-generation repeater family, integrated with six/eight 10/100 transceivers.

3361 LED

Abstract: LXT9880 ups transformer winding formula
Contextual Info: Cortina Systems LXT9860/LXT9880 Advanced 10/100 Repeater with Integrated Management Datasheet The Cortina Systems® LXT9860/LXT9880 Advanced 10/100 Repeater with Integrated Management LXT98x0 Repeater is the next-generation repeater family, integrated with six/eight 10/100 transceivers.

IC 93cs46

Contextual Info: noNm BR93CS46 PRELIMINARY 1024-Bit Serial 3V and 5V Electrically Erasable PROM The READ instruction uses an address pointer that automatically increments when all 16 bits in one register have been clocked out. tf docking continues, succes­ sive registers are accessed, allowing the BR93CS46

Contextual Info: SGS-THOMSON o m » iO T ô [ ï l S ST93CS46 SERIAL ACCESS CMOS 1K bit (64 x 16) EEPROM • MINIMUM 1,000,000 ERASE/WRITE CYCLES, WITH OVER 10 YEARS DATA RETENTION * SINGLE 3V TO 5.5V SUPPLY VOLTAGE ■ USER DEFINED WRITE PROTECT AREA ■ PAGE WRITE MODE (4 WORDS)

Y0803

Abstract: U0801B IC LM7805 N1 Y10 pin diagram of IC LM7805 C0801 STI3400 U0101 U0604 plx9060
Contextual Info: Q CL 7 D PR 3 4 14 2 U?A Q 5 CLK 6 {Value} 1 1 2 3 4 5 6 SPARE GATES: 8 ECN HISTORY DESCRIPTION REV 2 -ADD CDREQ DATE APPROVAL 10/24/95 U0101 PU0101 A PU0102 PU0103 12 11 D U0801B 9 Q CLK 8 Q 74ACT74 13 20V8C DIP 22 21 20 19 18 17 16 15 CL O1 IO2 IO3 IO4 IO5

0x9050 0x10b5

Abstract: 8BA22 LA2780 PLXMON95 10B5 BD28 MACH210 NM93CS46 9050RDK PLX9050
Contextual Info: PCI 9050RDK Development Kit Manual Version 1.2 January 28, 1998 Product Sales: 1- 800 -759-3735 Fax: 1- 408-774-2169 Email: info@plxtech.com Web and FTP Site: //www.plxtech.com T E C H N O L O G Y Table of Contents Preface . vii

140 XBE 10000

Abstract: pci9080 10B5 80960C 9060ES 9060SD 93CS46 93CS56 NM93CS46 NM93CS56
Contextual Info: PCI 9080 /EX— PCI I/O ACCELERATOR T E C H N O L O G Y l20 C O M P A T IB LE PCI BUS M A S T E R IN TE R F A C E C H IP FO R A D A P T E R S A N D E M B E D D E D S Y S T E M S JULY 24 ,1 9 9 7 VERSION 1.02 FEATURES 1. G EN ER A L D ESC R IPTIO N • PCI Version 2.1 compliant Bus Master Interface chip

ISP2032

Abstract: lattice isp2032 4380-0000 PLD-10 glb02 PU18 PU27 SK 9080 PAL16V8 MPC860
Contextual Info: PCI 9080/860 AN MPC860 PowerQUICC  to PCI bus Application Note January 5, 1998 Version 2.0 Features _ • • • Complete Application Note for designing a PCI adapter or embedded system based on the Motorola MPC860 PowerQUICC including:

eeprom d4x

Abstract: pci9080 9080 10B5 80960C 9060ES 9060SD 93CS46 93CS56 NM93C46
Contextual Info: PCI 9080 T E C H N O L O G Y PCI I/O ACCELERATOR l20 COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS SEPTEMBER 1 ,1 9 9 8 VERSION 1.05 FEATURES PCI <=> Local Data transfers up to 132 MB/sec • PCI Specification 2.1 v2.1 compliant Bus Master