IC 4050 DATA SHEET Search Results

4049

Abstract: CI 4049 hc4049 15-V C4049 C4050 CD54HC4049 CD54HC4050 CD74HC4049 CD74HC4050
Contextual Info: [ /Title CD74H C4049, CD74H C4050 /Subject (High Speed CMOS Logic Hex CD54HC4049, CD74HC4049, CD54HC4050, CD74HC4050 Data sheet acquired from Harris Semiconductor SCHS205G High-Speed CMOS Logic Hex Buffers, Inverting and Non-Inverting February 1998 - Revised December 2003

4049

Abstract: C4049 cd74hct4049 C4050 hc4049 15-V CD54HC4049 CD54HC4050 CD74HC4049 CD74HC4050
Contextual Info: [ /Title CD74H C4049, CD74H C4050 /Subject (High Speed CMOS Logic Hex CD54HC4049, CD74HC4049, CD54HC4050, CD74HC4050 Data sheet acquired from Harris Semiconductor SCHS205F High-Speed CMOS Logic Hex Buffers, Inverting and Non-Inverting February 1998 - Revised November 2003

CD74HC4049NSR

Abstract: CD74HC4049M
Contextual Info: [ /Title CD74H C4049, CD74H C4050 /Subject (High Speed CMOS Logic Hex CD54HC4049, CD74HC4049, CD54HC4050, CD74HC4050 Data sheet acquired from Harris Semiconductor SCHS205I High-Speed CMOS Logic Hex Buffers, Inverting and Non-Inverting February 1998 - Revised February 2005

pinout diagram of 4049

Contextual Info: [ /Title CD74H C4049, CD74H C4050 /Subject (High Speed CMOS Logic Hex CD54/74HC4049, CD54/74HC4050 Data sheet acquired from Harris Semiconductor SCHS205B High-Speed CMOS Logic Hex Buffers, Inverting and Non-Inverting February 1998 - Revised May 2000 Features

1RD3903

Abstract: IRD3899 IRD3901 IRD3903 IRD3909 IRD3913 355AT ir03899 10Qt
Contextual Info: Data Sheet No. PD-2.092 IN T ER N A TIO N A L R E C TIFIE R IR D 3 B S 9 , IR D 3 9 Q 9 IÖR S ER IES SO and 30 Amp Past Recovery Rectifier Diodes Description Major Ratings and Characteristics This range of fast recovery diodes is designed for applications in DC power supplies, inverters,

Contextual Info: [ /Title CD74H C4049, CD74H C4050 /Subject (High Speed CMOS Logic Hex CD54HC4049, CD74HC4049, CD54HC4050, CD74HC4050 Data sheet acquired from Harris Semiconductor SCHS205I High-Speed CMOS Logic Hex Buffers, Inverting and Non-Inverting February 1998 - Revised February 2005

Contextual Info: [ /Title CD74H C4049, CD74H C4050 /Subject (High Speed CMOS Logic Hex CD54HC4049, CD74HC4049, CD54HC4050, CD74HC4050 Data sheet acquired from Harris Semiconductor SCHS205I High-Speed CMOS Logic Hex Buffers, Inverting and Non-Inverting February 1998 - Revised February 2005

IC 4049

Abstract: ic 4050 pin diagram 4049 logic gate 4049 PC hct 4050 hct 4049 ic 4049 pinout cd74hc4050 4049 pin diagram
Contextual Info: CD74HC4049, CD74HC4050 h a f r f r is SEMIC0NDUCT0R High Speed CM OS Logic Hex Buffers, Inverting and Non-Inverting February 1998 Features Description • Typical Propagation Delay: 6ns at Vcc = 5V, C L = 15pF, Ta = 25°C The Harris CD74HC4049 and CD74HC4050 are fabricated

NCP18WF104F12RB

Abstract: NCP15WF104F03RC NCP15XH103F03RC k 2750 transistor NCP18XH103F03RB BF transistor series catalog NCP15WB473F03RC traffic light using 68K R01E thermistor ptc 15k ohm
Contextual Info: !Note • This PDF catalog is downloaded from the website of Murata Manufacturing co., ltd. Therefore, it’s specifications are subject to change or our products in it may be discontinued without advance notice. Please check with our sales representatives or product engineers before ordering.

CD74HC4049NSR

Contextual Info: [ /Title CD74H C4049, CD74H C4050 /Subject (High Speed CMOS Logic Hex CD54HC4049, CD74HC4049, CD54HC4050, CD74HC4050 Data sheet acquired from Harris Semiconductor SCHS205I High-Speed CMOS Logic Hex Buffers, Inverting and Non-Inverting February 1998 - Revised February 2005

AN1404

Abstract: AN1405 AND8020 MC100E336 MC100E336FN MC100E336FNR2
Contextual Info: MC100E336 5VĄECL 3ĆBit Registered Bus Transceiver The MC100E336 contains three bus transceivers with both transmit and receive registers. The bus outputs BUS0–BUS2 are specified for driving a 25 Ω bus; the receive outputs (Q0 – Q2) are specified for 50 Ω.

AN1404

Abstract: AN1405 AND8020 MC100E256 MC100E256FN MC100E256FNR2 D2D marking code
Contextual Info: MC100E256 5VĄECL 3ĆBit 4:1 MuxĆLatch The MC100E256 contains three 4:1 multiplexers followed by transparent latches with differential outputs. Separate Select controls are provided for the leading 2:1 mux pairs see logic symbol . When the Latch Enable (LEN) is LOW, the latch is transparent, and

E142 wafer format

Abstract: HEL32 MR 4710 IC 300w power amplifier circuit diagram HEL05 klt22 HEL12 HEL31 HEL16 HLT22 HLT28
Contextual Info: DL140/D Rev. 6, Jan-2001 High Performance ECL Data ECLinPS and ECLinPS Lite™ High Performance ECL Device Data ECLinPS, ECLinPS Lite, and Low Voltage ECLinPS DL140/D Rev. 6, Jan–2001  SCILLC, 2001 Previous Edition  2000 “All Rights Reserved”

MC100E154

Abstract: MC100E154FN MC100E154FNR2 MC10E154 MC10E154FN MC10E154FNR2
Contextual Info: MC10E154, MC100E154 5VĄECL 5ĆBit 2:1 MuxĆLatch The MC10E/100E154 contains five 2:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on

MC100E157

Abstract: MC100E157FN MC100E157FNR2 MC10E157 MC10E157FN MC10E157FNR2
Contextual Info: MC10E157, MC100E157 5VĄECL Quad 2:1 Multiplexer The MC10E/100E157 contains four 2:1 multiplexers with differential outputs. The output data are controlled by the individual Select SEL inputs. The individual select control makes the devices well suited for random logic designs.

MC10E155

Abstract: MC10E155FN MC10E155FNR2 MC100E155 MC100E155FN MC100E155FNR2
Contextual Info: MC10E155, MC100E155 5VĄECL 6ĆBit 2:1 MuxĆLatch The MC10E/100E155 contains six 2:1 multiplexers followed by transparent latches with single-ended outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic

MSM7570-01

Abstract: DTMF Tone Decoder vox switch MSM7570 MSM7570L-01 MSM7570L-02 MSM7590 MSM7590L-01
Contextual Info: APPLICATION NOTE O K I C O D E C P R O D U C T S Using the MSM7570/90 CODEC Evaluation Board September 1994 Author J. Sarma OKI Semiconductor reserves the right to make changes in specifications at anytime and without notice. This information furnished by

MC100E158

Abstract: MC100E158FN MC100E158FNR2 MC10E158 MC10E158FN MC10E158FNR2
Contextual Info: MC10E158, MC100E158 5VĄECL 5ĆBit 2:1 Multiplexer The MC10E/100E158 contains five 2:1 multiplexers with differential outputs. The output data are controlled by the Select input SEL . The 100 Series contains temperature compensation. • • • • • •

E212 transistor

Abstract: E112 E212 MC100E112 MC100E112FN MC10E112 MC10E112FN MC10E112FNR2 D200-400
Contextual Info: MC10E112, MC100E112 5VĄECL Quad Driver The MC10E/100E112 is a quad driver with two pairs of OR/NOR outputs from each gate, and a common, buffered enable input. Using the data inputs the device can serve as an ECL memory address fan-out driver. Using just the enable input, the device serves as a clock

MC100E160

Abstract: MC100E160FN MC100E160FNR2 MC10E160 MC10E160FN MC10E160FNR2
Contextual Info: MC10E160, MC100E160 5VĄECL 12ĆBit Parity Generator/Checker The MC10E/100E160 is a 12-bit parity generator/checker. The Q output is HIGH when an odd number of inputs are HIGH. A HIGH on the Enable input EN forces the Q output LOW. The 100 Series contains temperature compensation.

marking CODE D2B

Abstract: MC100E104 MC100E104FN MC100E104FNR2 MC10E104 MC10E104FN MC10E104FNR2 marking D3B ECL IC NAND
Contextual Info: MC10E104, MC100E104 5VĄECL Quint 2ĆInput AND/NAND Gate The MC10E/100E104 is a quint 2-input AND/NAND gate. The function output F is the OR of all five AND gate outputs, while F is the NOR. The Q outputs need not be terminated if only the F outputs are to be

E112

Abstract: E212 MC100E212 MC100E212FN MC100E212FNR2 MC10E212 MC10E212FN MC10E212FNR2 E212 transistor
Contextual Info: MC10E212, MC100E212 5VĄECL 3ĆBit Scannable Registered Address Driver The MC10E/100E212 is a scannable registered ECL driver typically used as a fan-out memory address driver for ECL cache driving. In a VLSI array based CPU design, use of the E212 allows the user to

E112

Abstract: E212 MC100E212 MC100E212FN MC100E212FNR2 MC10E212 MC10E212FN MC10E212FNR2
Contextual Info: MC10E212, MC100E212 5V ECL 3-Bit Scannable Registered Address Driver The MC10E/100E212 is a scannable registered ECL driver typically used as a fan-out memory address driver for ECL cache driving. In a VLSI array based CPU design, use of the E212 allows the user to

Contextual Info: MC10E142, MC100E142 5V ECL 9-Bit Shift Register The MC10E/100E142 is a 9-bit shift register, designed with byte-parity applications in mind. The E142 performs serial/parallel in and serial/parallel out, shifting in one direction. The nine inputs D0 − D8 accept parallel input data, while S-IN accepts serial input