IC 24 PIN Search Results

Contextual Info: TD62824P TD62824P 8 x 3 BIPOLAR DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC PARALLEL SHIFT REGISTER/DRIVER GENERAL DESCRIPTION The T D 6 2 8 2 4 P is a general purp o s e 24-bit driv e r IC c o n s i s t i n g of 8 b l o c k 3-bit shift regi s t e r and 24-bit driv e r open collector .

Contextual Info: Ordering number : ENN6974A CMOS IC LC72148V Electronic Tuning PLL Frequency Synthesizer for Car Stereo Systems Package Dimensions unit: mm 3175B-SSOP24 [LC72148V] 7.8 24 1 0.33 0.65 7.6 0.15 0.22 0.1 (1.3) • High-speed programmable divider — FMIN: 10 to 180 MHz . Pulse swallower technique

Contextual Info: .100" X .300" or .600" Molded DIP 877 Series Part o f a com plete cable assem bly M ates with industry standard IC sockets / .100 X .300 inch up to 20 positions and .100 X .600 inch betw een 24 and 40 positions One piece, m olded on construction with integral strain relief

Contextual Info: SN761646 www.ti.com SLES251 – NOVEMBER 2009 DIGITAL TV TUNER IC Check for Samples: SN761646 FEATURES 1 VHI RFIN UHF RFIN2 UHF RFIN1 GPP2 VHI OSC B 24 RF GND UHF OSC B2 2 23 MIXOUT2 OSC GND 3 22 MIXOUT1 CP 4 21 IF IN VTU 5 20 RFAGC OUT IF GND 6 19 SDA IF OUT

Contextual Info: HD74AC00 • Quad 2-Input NAND Gate Pin Assignment • O u tp uts Source/Sink 24 mA T op View DC Characteristics (u n le s s Sym bol Ic e o th e rw is e s p e c ifie d ) P a ra m e te r M ax C o n d itio n V in = V cc o r G ro u n d . M a x im u m Q u ie s c e n t

TI009

Contextual Info: 54AC11643, 74AC 11643 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS T I0095— D2957, JU LY 1987— REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11643 . . . JT PACKAGE 74AC11643 . . . DW OR NT PACKAGE TOP VIEW Center-Pin V c c and GND Configurations to

6SL7wgt

Abstract: 6Sl7 rs tube
Contextual Info: 6SL7WGT TUNO-SOL -TWIN TRIODE T W IN H IG H MU T R IO D E S C O A T E D U N IP O T E N T IA L C A T H O D E A N Y M O U N T IN G P O S IT IO N B O T T O M V IE W BASING DIAGRAM JEDEC 8BD G LASS B U L B IN T E R M E D IA T E S H E LL 8 PIN O C T A L B8-6

2N404

Abstract: MPS404 2n404a a5t404
Contextual Info: TYPES A5T404, A5T404A, A8T404, A8T404A P-N-P SILICON TRANSISTORS _B U L L E T I N N O . O L -S 7 3 1 1 9 7 9 , M A R C H 1973 SILECTt TRANSISTORS* FOR LOW-COST REPLACEMENT OF GERMANIUM 2N404, 2N404A • A5T404, A5T404A Have Standard TO-18 100-mil Pin-Circle Configuration

Contextual Info: ¥ it a c h i/ logic/arrays/m em 12 5ËJ n>ntan3 92D H D 74H C393 The H D 7 4 H C 3 9 3 10523 0010523 D • Dual 4-bit Binary Counters contain two 4-bit ripple carry binary | « /3 PIN ARRANG EM ENT counters, which can be cascaded to create a single divide-by256 counter.

50-12P1

Abstract: B3800 PS18 SV18 UH50A 42T120
Contextual Info: VDI 50-12P1 VII 50-12P1 VID 50-12P1 VIO 50-12P1 IC25 = 49 A = 1200 V VCES VCE sat typ. = 3.1 V IGBT Modules in ECO-PAC 2 Short Circuit SOA Capability Square RBSOA Preliminary data sheet VII VDI IK10 JK AC1 VID OP9 VIO L9 X15 SV18 X16 NTC F1 X16 Pin arangement see outlines

2a117

Contextual Info: 54AC11158, 74AC11158 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS TI010&— D 2957 JULY 1969— REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11158 . . . J PACKAGE 74AC11158 . . . DW OR N PACKAGE TOP VIEW Center-Pin V c c and GND Configurations to

237td

Contextual Info: VKI 50-06P1 IC25 = 42.5 A = 600 V VCES VCE sat typ. = 2.4 V IGBT Modules in ECO-PAC 2 Short Circuit SOA Capability Square RBSOA Preliminary data sheet F10 K10 A1 P18 K13 A4 D4 NTC H13 N9 B3 X18 L9 T16 O7 S18 Pin arangement see outlines Features Symbol Conditions

Contextual Info: ill# ICW0RKS Preliminary WB1225 Serial Input PLL with 2.5GHz Prescaler Figure 1 Pin Diagram Features IC W ORKS BiCMOS process 0r O SCJN NC Operating voltage 2.7V to 5.5V PWDN OSC_OUT Operating frequency: up to 2.5GHz 0p VP Lock detect feature Fout BISW v cc

Contextual Info: Preliminary ill# ICW 0RKS WB1332X Dual Serial Input PLL with 1.2GHz and 510MHz Prescalers Features Figure 1 • IC WORKS BiCMOS process Pin Diagram • Operating voltage 2.7V to 5.5V — LI Vcc2 • Operating frequency to 1,2GHz and 510MHz with inputs of - 1 5dBm and Vcc of 3.0V

Contextual Info: Preliminary GaAs IC 5 Bit Digital Attenuator With Serial-to-Parallel Driver DC–2 GHz AA107-310 Features MLF 5 x 5 -310 • Positive Voltage Operation (+5 V) 0.197 (5.00 mm) BSC 0.039 (1.00 mm) MAX. PIN 1 0.187 0.001 INDICATOR (4.75 mm) BSC (0.025 mm) 32

74AC11873

Contextual Info: 54AC11873, 74AC11873 DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS • 54A C 11 8 73 . . . J T P A C K A G E 3-State Buffer-Type Outputs Drive Bus 74AC 11B73 . . . D W OR N T P A C K A G E Lines Directly TOP V IE W • Bus-Structured Pinout • Flow -Through A rchitecture O ptim izes PCB

E15031

Abstract: e15028 e15029 mje15030 mje15031 je15029 JE15031 MJE15028 MJE15029 MJE15030 MJE15031
Contextual Info: MJE15028, MJE15030 MJE15029, MJE15031 MJE15028,15030 MJE15029,15031 NPN PLASTIC POWER TRANSISTORS PNP PLASTIC POWER TRANSISTORS High frequency Drivers in Audio Amplifiers PIN CONFIGURATION 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR L 4 DIM A B C E F G H

Contextual Info: UT54ACS193/UT54ACTS193 Radiation-Hardened Synchronous 4-Bit Up-Down Dual Clock Counters FEATURES • • • • • • • • • • PIN OUTS 16-Pin D IP Top View Look-ahead circuitry enhances cascaded counters Fully synchronous in count modes Parallel asynchronous load for modulo-N count lengths

Contextual Info: HITACHI/ LOGIC/ARRAYS/MEUTS DËJ44^203 DGIOSYSÛf 92D HD74HC670 10575 D T 'V t - o ? - o s ~ 9 4-by-4 R e giste r File with 3-state outputs T h e H D 7 4 H C 6 7 0 , 16-bit register file is organized as 4 w o rd s PIN ARRANGEMENT o f 4 bits each and separate on -ch ip d ecod in g is p ro vid e d fo r

AA101-80

Abstract: SSOP-16
Contextual Info: GaAs IC 5 Bit Digital Attenuator 1 dB LSB Positive Control 0.5–2.5 GHz AA101-80 Features SSOP-16 • Attenuation 1 dB Steps to 31 dB with High Accuracy 0.197 5.00 mm 0.189 (4.80 mm) 0.025 (0.635 mm) TYP. PIN 16 ■ Single Positive Control (+3 to +5 V) for

D-68623

Contextual Info: VWI 15-12P1 IC25 IGBT Module VCES VCE sat typ. Sixpack in ECO-PAC 2 S9 Preliminary data L9 N5 = 18 A = 1200 V = 2.3 V K 12 N9 R5 NTC X 18 W 14 J 13 A5 D5 H5 A1 F3 C1 K 10 G1 Pin arangement see outlines Features IGBTs Conditions Maximum Ratings VCES TVJ = 25°C to 150°C

Contextual Info: CY54FCT480T, CY74FCT480T DUAL 8-BIT PARITY GENERATORS/CHECKERS SCCS025B – MAY 1993 – REVISED OCTOBER 2001 D D D D D D D D D D D Function, Pinout, and Drive Compatible With FCT and F Logic Reduced VOH Typically = 3.3 V Versions of Equivalent FCT Functions

38PIN

Contextual Info: SN761677 www.ti.com SLES066A – DECEMBER 2002 TV/VCR TUNER IC WITH DC/DC CONVERTER FEATURES D Single Chip Mixer/Oscillator, Synthesizer, and DA PACKAGE TOP VIEW 38-PIN TSSOP (DA) 30-V DC/DC Converter for Tuning Amplifier D D D D D VHF-L, VHF-H, UHF 3-Band Local Oscillator

Contextual Info: “H Y U N D A I HYM536A410A M-Series 4M X 36-bit CMOS DRAM MODULE DESCRIPTION The HYM536A41OA is a 4M x 36-bit Fast page mode CMOS DRAM module consisting of nine HY5117400A in 24/26 pin SOJ on a 72 pin glass-epoxy printed circuit board. 0.22^F decoupling capacitor is mounted for each DRAM.