I486 SL Search Results

82353

Abstract: intel 82358 82359 82353 intel intel 82353 82358DT
Contextual Info: 82353 ADVANCED DATA PATH • Dual Port Architecture Allows Host to Access Memory without Incurring EISA Arbitration ■ Provides Optimal i486 Burst Performance ■ High Performance, Flexible Memory Support: — Designed as a 16-Bit Slice which Interfaces 16, 32, or 64-Bit Memory

Contextual Info: IS61C632A m i 32K x 32 SYNCHRONOUS PIPELINED STATIC RAM SEPTEMBER 1997 FEATURES DESCRIPTION • The I S S I IS61C632A is a high-speed, low-power synchro­ nous static RAM designed to provide a burstable, highperformance, secondary cache for the i486 , Pentium™,

Contextual Info: IS ffl 32K x 32 SYNCHRONOUS FAST STATIC RAM PRELIMINARY JUNE 1997 FEATURES DESCRIPTION • Fast access tim e: The ISSI IS61C632A is a high-speed, low-power synchro­ nous static RAM designed to provide a burstable, highperformance, secondary cache for the i486 , Pentium™,

Contextual Info: IS M 64K x 36 SYNCHRONOUS PIPELINED STATIC RAM ADVANCE INFORMATION JULY 1997 FEATURES DESCRIPTION • Internal self-timed write cycle The IS S IIS61SP6436 is a high-speed, low-power synchro­ nous static RAM designed to provide a burstable, highperformance, secondary cache for the i486 , Pentium™,

Contextual Info: m IS61SP6464 64Kx 64 SYNCHRONOUS PIPELINE STATIC RAM i ADVANCE INFORMATION MARCH 1997 FEATURES DESCRIPTION • Fast access time: The I S S I IS61SP6464 is a high-speed, low-power synchro­ nous static RAM designed to provide a burstable, highperformance, secondary cache for the i486 , Pentium™,

Contextual Info: ISSI IS61SF6436 64Kx 36 SYNCHRONOUS FLOW-THROUGH STATIC RAM ADVANCE INFORMATION JUNE 1998 FEATURES DESCRIPTION • Fast access times: 8.5 ns, 9 ns, 10 ns The IS S I IS61SF6436 is a high-speed, low-power synchro­ nous static RAM designed to provide a burstable, highperformance, secondary cache for the i486 , Pentium™,

Contextual Info: IS 6 1 C 6 3 2 A m s 32K x 32 SYNCHRONOUS PIPELINED STATIC RAM MAY 1998 FEATURES DESCRIPTION • Fast access time: The I S S I IS61C632A is a high-speed, low-power synchro­ nous static RAM designed to provide a burstable, highperformance, secondary cache for the i486 , Pentium™,

Contextual Info: IB M 0 4 1 8 1 2 P Q K B Preliminary 6 4 K X 18 BURST SRAM Features • 64K x 18 Synchronous Burst Mode SRAM • 5 V Tolerant I/O • 0.5n CMOS Technology • Asynchronous Output Enable • Compatible with Pentium and i486™ proces­ sors • Self-Timed Write Operation and Byte Write

Contextual Info: P R U tflO G O M V in te i l n t e l 486 TM DX CPU-CACHE CHIP SET 50 MHz Intel486 DX Microprocessor, 82495DX Cache Controller, and 82490DX Dual Ported Intelligent Cache SRAM • 50 MHz Intel486™ DX CPU — RISC Integer Core with Frequent Instructions Executing in One Clock

Contextual Info: DASH NO. M CODE R E V IS IO N S MADE FROM ISSUE CHANGES KC—59—486 CN 3 7 1 1 3 D REDRAWN KH 0 9 / 1 2 / 9 6 6 I-486 1. 2. 3. 4. FOR USE WITH TIMES E M -5 9 CABLE. FOR CABLING INSTRUCTIONS SEE C P -4 6 5 . FOR CRIMPING USE DIE SIZE K T H -20 0 2. MATERIALS:

R36100

Abstract: crt terminal interface block diagram serial controller 85c30 Centronics connector ethernet 85C30 schematic schematic sim Centronics connector drawing 85C30 DP83932 R4700
Contextual Info: R36100 EVALUATION AND DEVELOPMENT PLATFORM 79S361 Product Brief Integrated Device Technology, Inc. FEATURES • Dual serial ports through R36100 internal UART or 85C30 external UART • Provides for logic analyzer connection • Expansion connector allows all CPU signals to be

Contextual Info: IB M 0 4 1 8 1 3 P Q K B P relim inary 64K X 18 B U R ST P IP ELIN E SR A M Features • 64K x 18 Organization • Registered Addresses, Data Ins, Control sig­ nals, and Outputs • 0.5n CMOS Technology • Asynchronous Output Enable • Synchronous Burst Mode of Operation Compati­

SO56-2

Contextual Info: IDT54/74FCT162701T/AT FAST CMOS 18-BIT READ/WRITE BUFFER MILITARY AND COMMERCIAL TEMPERATURE RANGES FAST CMOS 18-BIT READ/WRITE BUFFER DESCRIPTION: FEATURES: − − − − − − − − − − − − − − IDT54/74FCT162701T/AT 0.5 MICRON CMOS Technology

celeron 600

Abstract: pentium ULV INTELDX4 PROCESSOR MOBILE Intel SSE2 pentium 4 Intel SSE2 celeron Intel 2004 celeron D i486 Processor Specification Update 1102v2
Contextual Info: R Ultra Low Voltage Intel Celeron® M Processor at 600 MHz Addendum to the Intel® Celeron® M Processor Datasheet June 2004 Revision 2.0 Document Number: 301753 R INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE,

Contextual Info: CY7C1339G PRELIMINARY 4-Mbit 128K x 32 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 128K x 32 common I/O architecture • 3.3V core power supply • 2.5V / 3.3V I/O operation • Fast clock-to-output times

M6SS

Contextual Info: bbE D INTEGRATE» DEVICE M6SS771 G01E37T Ti|b • IDT CMOS CacheRAM 32k x 9-BIT 288K-BIT BURST COUNTER & SELF-TIMED WRITE IDT71589SA FEATURES: DESCRIPTION: • • • • • • • The IDT71589 is a very high-speed 32k x 9-bit static RAM with full on-chip hardware support of the 80486 CPU interface.

Contextual Info: IDT79R3020 RISC CPU WRITE BUFFER Integrated D evice Tech no logy, Inc. FEATURES: DESCRIPTION: • T e m porary storage bu ffers to en hance the perform ance of the ID T79R 3000 R ISC C P U processor • A llo w s for w rite operatio ns by the R IS C C P U processor

Contextual Info: CY7C1338G 4-Mbit 128 K x 32 Flow-Through Sync SRAM 4-Mbit (128 K × 32) Flow-Through Sync SRAM Features 8.0 ns (100-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated

Contextual Info: INTEGRATED DEVICE tfc,E D • 4A25771 0012317 Tbl ■ H>T BiCMOS CacheRAM 32k x 9-BIT 288k-BIT BURST COUNTER & SELF-TIMED WRITE PRELIMINARY IDT71B589S FEATURES: DESCRIPTION: • • • • • • • • • The IDT71B589 is a very high-speed 32k x 9-bit static RAM

SO56-2

Contextual Info: IDT54/74FCT162701T/AT FAST CMOS 18-BIT R/W BUFFER Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • • • • The FCT162701T/AT is an 18-bit Read/Write buffer with a four deep FIFO and a read-back latch. It can be used as a read/write buffer between a CPU and memory or to

Contextual Info: CY7C1329H 2-Mbit 64 K x 32 Pipelined Sync SRAM 2-Mbit (64 K × 32) Pipelined Sync SRAM Features Functional Description • Registered inputs and outputs for pipelined operation The CY7C1329H SRAM integrates 64 K × 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter

Contextual Info: CY7C1368C 9-Mbit 256 K x 32 Pipelined DCD Sync SRAM 9-Mbit (256 K × 32) Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation ■ Optimal for performance (double-cycle deselect) ❐ Depth expansion without wait state

lfl 1.635

Contextual Info: BO liinA R/W HITE TECHNOLOGY 50E D o o n o s ia TTWhite Technology, Inc. A18C 1 A16 E 2 A14C 3 A12 E 4 A7E 5 A6 E 6 A5 E 7 A4 C 8 A3 C 9 A2 E 10 A1E A0E i/o o E 1/01 E W 3 m • b u MEMORY PRODUCTS WS-512K8 PC 32 □ v œ 31 □ A15 30 H A17 512K x 8 BIT CMOS SRAM Module

Contextual Info: PRELIMINARY PDM34089 3.3V 64K x 32 Fast CMOS Synchronous Static RAM with Burst Counter Features n n n n n n n n n n n n n n n Interfaces directly with the x86, Pentium , 680X0 and PowerPC™ processors Single 3.3V power supply Mode selectable for interleaved or linear burst: