HYMP125 Search Results

HY5PS1G421

Abstract: DDR2-400 DDR2-533 PC2-3200 PC2-4300 RA13 M4C5 M4C5 1
Contextual Info: 256Mx72 bits DDR2 SDRAM Registered DIMM HYMP125R72 L M4 Revision History No. 0.1 0.2 History Draft Date Initial Release Mar. 2004 Corrected IDD Spec. May. 2004 Corrected Pin assignment table & SPD typo(#42) July 2004 Remark This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

HYMP125P72AP4-C4

Abstract: HYMP125P72AP4-E3 HYMP125P72AP4-S5 HYMP125P72AP4-Y5 HYNIX rDIMM
Contextual Info: SERIAL PRESENCE DETECT HYMP125P72AP4-E3 Function described HYMP125P72AP4-C4 HYMP125P72AP4-Y5 HYMP125P72AP4-S5 Function support HEX Function support HEX Function support HEX Function support HEX Number of SPD Bytes Written during Module Production 128 Bytes

HYMP125R72AP4-C4

Abstract: HYMP125R72AP4-E3
Contextual Info: SERIAL PRESENCE DETECT HYMP125R72AP4-E3 Function described HYMP125R72AP4-C4 Function support HEX Function support HEX Number of SPD Bytes Written during Module Production 128 Bytes 80 128 Bytes 80 1 Total Number of Bytes in SPD Device 256 Bytes 08 256 Bytes

DDR2-400

Abstract: DDR2-533 DDR2-667 MO-237 PC2-3200 PC2-4300 PC2-5300
Contextual Info: 256Mx72 bits DDR2 SDRAM Registered DIMM HYMP125R72 L 4 Revision History No. 0.1 Details Draft Date Initial release May. 2004 Corrected Pin assignment table Nov. 2004 Remark This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

Contextual Info: HYMP125R72M4-E3/C4 SERIAL PRESENCE DETECT E3 Function described 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Number of SPD Bytes Written during Module Production

HYMP125U72AP8-Y5

Abstract: HYNIX manufacturing code HYMP125U72AP8-C4 HYMP125U72AP8-E3 HYMP125U72AP8-S5 udimm HYNIX lot date code
Contextual Info: SERIAL PRESENCE DETECT HYMP125U72AP8-E3 Function described HYMP125U72AP8-C4 HYMP125U72AP8-Y5 HYMP125U72AP8-S5 Function support HEX Function support HEX Function support HEX Function support HEX Number of SPD Bytes Written during Module Production 128 Bytes

HYMP125U72P8-E3

Contextual Info: HYMP125U72P8-E3/C4 SERIAL PRESENCE DETECT E3 Function described 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58~61 62 63 Number of SPD Bytes Written during Module Production

DDR2-400

Abstract: DDR2-533 DDR2-667 MO-237 PC2-3200 PC2-4300 PC2-5300 HY5PS1G831
Contextual Info: 256Mx72 bits DDR2 SDRAM Registered DIMM HYMP125R72 L 8 Revision History No. 0.1 History Draft Date Defined target spec. May. 2004 Corrected Pin assignment table Nov. 2004 Remark This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

Contextual Info: 256Mx72 bits DDR2 SDRAM Registered DIMM HYMP125R72 L M4 Revision History No. 0.1 0.2 History Draft Date Initial Release Mar. 2004 Corrected IDD Spec. May. 2004 Corrected Pin assignment table & SPD typo(#42) July 2004 Remark This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

HYMP125U64

Abstract: DDR2-400 ECC hynix HYMP125U72
Contextual Info: 256Mx64 / 256Mx72 bits Unbuffered DDR2 SDRAM DIMM HYMP125U64 L 8/HYMP125U72(L)8 Revision History No. History Draft Date 0.1 Defined target spec. May. 2004 Remark This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

Contextual Info: 256Mx72 bits DDR2 SDRAM Registered DIMM HYMP125R72 L 8 Revision History No. History Draft Date 0.1 Defined target spec. May. 2004 Remark This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

Contextual Info: 256Mx72 bits DDR2 SDRAM Registered DIMM HYMP125R72 L M4 Revision History No. History Draft Date 0.1 Initial Release Mar. 2004 0.2 Corrected IDD Spec. & SPD typo (byte #22,#30) May. 2004 Remark This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

Contextual Info: 256Mx72 bits DDR2 SDRAM Registered DIMM HYMP125R72 L 4 Revision History No. Details Draft Date 0.1 Initial release May. 2004 Remark This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

HYMP125U64

Contextual Info: HYMP125U64P8-E3/C4 SERIAL PRESENCE DETECT E3 Function described 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58~61 62 63 Number of SPD Bytes Written during Module Production

HYMP125U72

Contextual Info: HYMP125U728-E3/C4 SERIAL PRESENCE DETECT E3 Function described 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58~61 62 63 Number of SPD Bytes Written during Module Production

HYMP125R72MP4-E3

Contextual Info: HYMP125R72MP4-E3/C4 SERIAL PRESENCE DETECT E3 Function described 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Number of SPD Bytes Written during Module Production

Contextual Info: 256Mx72 bits DDR2 SDRAM Registered DIMM HYMP125R72 L M4 DESCRIPTION Preliminary Hynix HYMP125R72(L)M4 series is registered 240-pin double data rate 2 Synchronous DRAM Dual In-Line Memory Modules(DIMMs) which are organized as 256Mx72 high-speed memory arrays. Hynix HYMP125R72(L)M4 series

HYMP125R72P4-E3

Abstract: 2c39 39AE hymp125r72p4
Contextual Info: HYMP125R72P4-E3/C4 SERIAL PRESENCE DETECT E3 Function described 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Number of SPD Bytes Written during Module Production

Contextual Info: 240pin DDR2 SDRAM Unbuffered DIMMs based on 1Gb 1st ver. This Hynix unbuffered Dual In-Line Memory Module DIMM series consists of 1Gb 1st ver. DDR2 SDRAMs in Fine Ball Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1Gb 1st ver. based DDR2 Unbuffered DIMM

HYMP151F72CP8

Abstract: HYMP151F72CP4
Contextual Info: 240pin Fully Buffered DDR2 SDRAM DIMMs based on 1Gb C-ver. This Hynix’s Fully Buffered DIMM is a high-bandwidth & large capacity channel solution that has a narrow host interface. Hynix’s FB-DIMM features novel architecture including the Advanced Memory Buffer that

23/HMP125U7EFR8C-C4/Y5/S6/S5

Contextual Info: 240pin Registered DDR2 SDRAM DIMMs based on 1Gb version C This Hynix Registered Dual In-Line Memory Module DIMM series consists of 1Gb version C DDR2 SDRAMs in Fine Ball Grid Array (FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1Gb version C based Registered DDR2 DIMM series provide a high performance 8 byte interface in 5.25" width

HYMP351R72MP4-E3

Contextual Info: 240pin Registered DDR2 SDRAM DIMMs based on 1Gb 1st ver. This Hynix unbuffered Dual In-Line Memory Module DIMM series consists of 1Gb 1st ver. DDR2 SDRAMs in Fine Ball Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1 Gb 1st ver. based Registered DDR2 DIMM series provide a high performance 8 byte interface in 5.25"

HYMP125U72CP8

Abstract: HYMP125U64cp HYMP125U72CP8-C4/Y5/S6/S5
Contextual Info: 240pin DDR2 SDRAM Unbuffered DIMMs based on 1Gb C version This Hynix unbuffered Dual In-Line Memory Module DIMM series consists of 1Gb version C DDR2 SDRAMs in Fine Ball Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1Gb version C based DDR2 Unbuffered DIMM series provide a high performance 8 byte interface in 133.35mm

HYMP125P72CP8

Abstract: HYMP151P72CP4 DDR2-400 DDR2-533 HYMP31G
Contextual Info: 240pin Registered DDR2 SDRAM DIMMs based on 1Gb version C This Hynix Registered Dual In-Line Memory Module DIMM series consists of 1Gb version C DDR2 SDRAMs in Fine Ball Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1Gb version C based Registered DDR2 DIMM series provide a high performance 8 byte interface in 5.25" width