HP8665A Search Results

Contextual Info: SN75LVDS84A FLATLINK TRANSMITTER SLLS354C – MAY 1999 – REVISED NOVEMBER 1999 D D D D D D D D D D D D 21:3 Data Channel Compression at up to 196 Million Bytes per Second Throughput Suited for SVGA, XGA, or SXGA Data Transmission From Controller to Display

LVDS93

Contextual Info: SN65LVDS93A www.ti.com. SLLS992 – AUGUST 2009 FLATLINK TRANSMITTER

LVDS83B

Abstract: SN65LVDS83B lvds83 SN75LVDS83B SN75LVDS83B routing signal generator rf marking Y2 24-bpc SN65LVDS83BZQL
Contextual Info: SN75LVDS83B www.ti.com . SLLS846 – MAY 2009 FLATLINK TRANSMITTER

Contextual Info: SN65LVDS93 www.ti.com . SLLS302G – MAY 1998 – REVISED MAY 2009 LVDS SERDES TRANSMITTER FEATURES

Contextual Info: SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.com FLATLINK TRANSMITTER Check for Samples: SN75LVDS83A FEATURES 1 • 2 • • • • • • • • LVDS Display Serdes Interfaces Directly to LCD Display Panels with Integrated LVDS Package Options: 8.1mm x 14mm TSSOP

DS90CR286

Abstract: SN65LVDS93 SN65LVDS94 SN65LVDS95
Contextual Info: SN65LVDS94 LVDS SERDES RECEIVER SLLS298E – MAY 1998 – REVISED FEBRUARY 2000 D D D D D D D D D D D D D D 4:28 Data Channel Expansion at up to 1.820 Gigabits per Second Throughput Suited for Point-to-Point Subsystem Communication With Very Low EMI 4 Data Channels and Clock Low-Voltage

DS90C581

Abstract: DTS2070C HP8656B HP8665A SN75LVDS82 SN75LVDS83 SN75LVDS86
Contextual Info: SN75LVDS83 FLATLINK TRANSMITTER SLLS271 – MARCH 1997 D D D D D D D D D D D D D D 28:4 Data Channel Compression at up to 227.5 Million Bytes per Second Throughput Suited for SVGA, XGA, or SXGA Display Data Transmission From Controller to Display With Very Low EMI

DS90C581

Abstract: DTS2070C HP8656B HP8665A SN75LVDS82 SN75LVDS83 SN75LVDS86
Contextual Info: SN75LVDS83 FLATLINK TRANSMITTER SLLS271C – MARCH 1997 – REVISED JULY 2000 D D D D D D D D D D D D D D 28:4 Data Channel Compression at up to 227.5 Million Bytes per Second Throughput Suited for SVGA, XGA, or SXGA Display Data Transmission From Controller to

D1713

Abstract: DS90CF363A HP8665A SN75LVDS82 SN75LVDS84 SN75LVDS84A
Contextual Info: SN75LVDS84A FLATLINK TRANSMITTER SLLS354D – MAY 1999 – REVISED AUGUST 2000 D D D D D D D D D D D D 21:3 Data Channel Compression at up to 196 Million Bytes per Second Throughput Suited for SVGA, XGA, or SXGA Data Transmission From Controller to Display

S221253

Abstract: HP8665A VP215
Contextual Info: DATA SHEET BIPOLAR DIGITAL INTEGRATED CIRCUIT µPB1510GV 3.0 GHz INPUT DIVIDE BY 4 PRESCALER IC FOR DBS TUNERS DESCRIPTION The µPB1510GV is a 3.0 GHz input divide by 4 prescaler IC for DBS tuner applications. This IC is suitable for use of frequency divider for PLL synthesizer block. This IC is a shrink package version of the µPB585G so that this small

Contextual Info: SN65LVDS96 N-LINK RECEIVER S L L S 2 9 6 A - MAY 1998 - R EVISED - N O VE M B ER 1998 • • • • 3:21 Data Channel Expansion at up to 1.3 Gigabits per Second Throughput Suited for Point-to-Point Subsystem Communication With Very Low EMI 3 Data Channels and Clock Low-Voltage

Contextual Info: SN65LVDS96 LVDS SERDES RECEIVER S LLS 296C - MAY 1 9 9 8 - R E V IS E D - FEB R U AR Y 1999 • • • • 3:21 Data Channel Expansion at up to 1.3 Gigabits per Second Throughput Suited for Point-to-Point Subsystem Communication With Very Low EMI 3 Data Channels and Clock Low-Voltage

Contextual Info: 3.0 GHz DIVIDE BY 2 PRESCALER FEATURES UPB1508GV INTERNAL BLOCK DIAGRAM • HIGH FREQUENCY OPERATION TO 3 GHz • FIXED DIVIDE RATIO: ÷2 • LOW CURRENT CONSUMPTION: 12 mA at 5 V IN D CLK IN CLK • SMALL PACKAGE: 8 pin SSOP • AVAILABLE IN TAPE AND REEL

Contextual Info: SN65LVDS94 www.ti.com SLLS298F – MAY 1998 – REVISED JANUARY 2006 LVDS SERDES RECEIVER FEATURES • • • • • • • • • • • • • • 4:28 Data Channel Expansion at up to 1.904 Gigabits per Second Throughput Suited for Point-to-Point Subsystem

Contextual Info: SN65LVDS96 www.ti.com SLLS296H – MAY 1998 – REVISED JULY 2006 LVDS SERDES RECEIVER FEATURES • • • • • • • • • • • • • • 3:21 Data Channel Compression at up to 1.428 Gigabits/s Throughput Suited for Point-to-Point Subsystem Communication With Very Low EMI

Contextual Info: SN65LVDS95ĆQ1 LVDS SERDES TRANSMITTER SGLS207A − OCTOBER 2003 − REVISED MAY 2008 DGG PACKAGE TOP VIEW D Qualified for Automotive Applications D 21:3 Data Channel Compression at up to 1.36 Gigabits per Second Throughput D4 VCC D5 D6 GND D7 D8 VCC D9

Contextual Info: SN75LVDS84A, SN65LVDS84AQ FLATLINK TRANSMITTER SLLS354E – MAY 1999 – REVISED JANUARY 2001 D D D D D D D D D D D D D 21:3 Data Channel Compression at up to 196 Million Bytes per Second Throughput Suited for SVGA, XGA, or SXGA Data Transmission From Controller to Display

SN75LVDS81

Abstract: SN75LVDS85 DS90C582 HP8656B SN75LVDS82 SN75LVDS84
Contextual Info: SN75LVDS82 FLATLINK RECEIVER SLLS259D – NOVEMBER 1996 – REVISED MAY 1999 D D D D D D D D D D D D 4:28 Data Channel Expansion at up to 227.5 Million Bytes per Second Mbytes/s Throughput Suited for SVGA, XGA, or SXGA Display Data Transmission From Controller to

DS90CR215

Abstract: HP8656B HP8665A SN65LVDS95 SN65LVDS96
Contextual Info: SN65LVDS95 LVDS SERDES TRANSMITTER SLLS297G – MAY 1998 – REVISED JUNE 2002 D D D D D D D D D D D D D D DGG PACKAGE TOP VIEW 21:3 Data Channel Compression at up to 1.36 Gigabits per Second Throughput Suited for Point-to-Point Subsystem Communication With Very Low EMI

DS90CR286

Abstract: SN65LVDS93 SN65LVDS94 SN65LVDS95
Contextual Info: SN65LVDS94 LVDS SERDES RECEIVER SLLS298E – MAY 1998 – REVISED FEBRUARY 2000 D D D D D D D D D D D D D D 4:28 Data Channel Expansion at up to 1.904 Gigabits per Second Throughput Suited for Point-to-Point Subsystem Communication With Very Low EMI 4 Data Channels and Clock Low-Voltage

Contextual Info: SN65LVDS96 LVDS SERDES RECEIVER SLLS296G – MAY 1998 – REVISED JUNE 2002 D D D D D D D D D D D D D D 3:21 Data Channel Expansion at up to 1.3 Gigabits per Second Throughput Suited for Point-to-Point Subsystem Communication With Very Low EMI 3 Data Channels and Clock Low-Voltage

DS90CR216

Abstract: HP8656B SN65LVDS95 SN65LVDS96 slls296g
Contextual Info: SN65LVDS96 www.ti.com SLLS296G – MAY 1998 – REVISED JUNE 2002 LVDS SERDES RECEIVER FEATURES • • • • • • • • • • • • • • 3:21 Data Channel Expansion at up to 1.3 Gigabits per Second Throughput Suited for Point-to-Point Subsystem

SN75LVDS81

Abstract: DTS2070C HP8656B HP8665A SN75LVDS86
Contextual Info: SN75LVDS86 FLATLINK RECEIVER SLLS268C – MARCH 1997 – REVISED MAY 1999 D D D D D D D D D D D D D 3:21 Data Channel Expansion at up to 163 Million Bytes per Second Throughput Suited for SVGA, XGA, or SXGA Display Data Transmission From Controller to Display With Very Low EMI

371j

Contextual Info: BIPOLAR DIGITAL INTEGRATED CIRCUIT UPB1510GV 3.0 GHz INPUT DIVIDE BY 4 PRESCALER IC FOR DBS TUNERS DESCRIPTION The UPB1510GV is a 3.0 GHz input divide by 4 prescaler IC for DBS tuner applications. This IC is suitable for use of frequency divider for PLL synthesizer block. This IC is a shrink package version of the µPB585G so that this small