HP181 Search Results

MIL-STD-883-compliant

Abstract: pipelined adder
Contextual Info: EP1810 EPLD High-performance, 48-macrocell Classic EPLD Combinatorial speeds with t PD as low as 20 ns - Counter frequencies of up to 50 MHz - Pipelined data rates of up to 62.5 MHz Programmable I/O architecture with up to 64 inputs or 48 outputs The following devices are pin-, function-, and programming filecompatible: EP1810, EP1810T, and EP1810 MIL-STD-883-compliant

Contextual Info: ANbrt r*a\ EP1810 EPLDs High-Performance 48-Macrocell Devices September 1991, ver. 2 Features Data Sheet □ □ □ □ □ □ □ □ □ □ General Description tPD The EP1810 Erasable Program m able Logic Devices E P L D s offer L S I density, TTL-equivalent speed, and low power consumption. Each E P L D can

H808

Abstract: HC02 09-65-1021 103026 26-48-1026
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