HEX S-R LATCH Search Results

Contextual Info: r r u im i _LTC1045M/883 Programmable Micropower Hex Translator/Receiver/Driver TECHNOLOGY flßsoiuTC mnximum r r t i r g s D€SCRIPTIOf1 Notes 1 and 2 The LTC1045M/883 is a hex level translator manufactured using Linear Technology’s enhanced LTCMOS silicon

Contextual Info: TECHNOLOGY Programmable Micropower Hex Translator / Receiver / Driver L i n t A B E £ ] 2 f £ FC R TU R C S D C S C R IP T IO n • ■ ■ ■ ■ ■

Contextual Info: u n m _ l i c i m TECHNOLOGY 5 P ro g ra m m a b le M ic ro p o w e r Hex Translator/ R eceive r/D river FCnTURCS D C S C R IP TIO n • ■ ■ ■ ■ ■ ■ ■ The LTC 1045 is a hex level translator manufactured using

MICRO-12

Abstract: prom 256x4 bit HD-6101 HD-6435 HD-6436 HD-6440 HD-6495 HM-6100 HM-6322 HM-6661
Contextual Info: C M O S Bus D r iv e r F a m ily HD-6435 CMOS HEX RESETTABLE LATCHED BUS D R IVER TRUTH TABLE FUNCTIONAL DIAGRAM FEATURES C O N T R O L IN P U T S Ri • S IN G L E POWER SU PPLY R2 El E2 L1 L2 H l-Z • H IG H N O IS E IM M U N IT Y • IN D U S T R IA L

CERAMIC DISK CAPACITOR

Abstract: HD-6435 3151v
Contextual Info: HD-6435 H A R IR IS S lS L S l! S E M IC O N D U C T O R P R O D U C T S D IV IS IO N CM O S HEX RESETTABLE LATCHED BUS DRIVER A DIVISION Of HARRIS CORPORATION Pinout Features S IN G L E P O W E R S U P P L Y 3V q 1 H IG H N O IS E IM M U N I T Y 2y C 2 IN D U S T R IA L A N D M IL IT A R Y G R A D E S

Contextual Info: 74ACT11378 HEX D-TYPE FLIP-FLOP WITH CLOCK ENABLE S C A S 1 8 5 A - A U G U S T 1990 - R EVISED A P R IL 1993 DW OR N PACKAGE • Inputs Are TTL-Voltage Compatible TOP VIEW • Contains Six D-Type Flip-Flops

LVC04A

Abstract: SN54LVC04A SN74LVC04A
Contextual Info: SN54LVC04A, SN74LVC04A HEX INVERTERS S C A S 281F - JA N U A R Y 1993 - R EVISED S E P TE M B E R 1997 • E P IC Enhanced-Performance Implanted CMOS Submicron Process • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)

Contextual Info: SN54LV04A, SN74LV04A HEX INVERTERS S C L S 3 8 8 B -S E P T E M B E R 1997 - R EVISED JU NE 1998 • • EP/C Enhanced-Performance Implanted CMOS Process SN54LV04A. . . j o r w SN 74LV04A . . . d , d b , d g v , n s , (TOP VIEW) Typical V q lp (Output Ground Bounce)

hd data separator

Abstract: HD-6101 HD-6431 HD-6432 HD-6433 HD-6434 HM-6100 HM-6322 HM-6661 6433 B
Contextual Info: C M O S B us D r iv e r F a m ily HD-6431 CMOS HEX LATCHING BUS D RIVER TRUTH TABLE FUNCTIONAL DIAGRAM FEATURES S IN G L E POWER SU PPLY H IG H N O ISE IM M U N IT Y IN D U S T R IA L G RADES AND D R IV E C A P A C IT Y M IL IT A R Y . . . . SO UR CE C U R R E N T

SN74LVC04A

Contextual Info: SN74LVC04A HEX INVERTER SC A S 281C - JA N U A R Y 1993 - R EVISED S E P TE M B E R 1996 • EPIC Enhanced-Performance Implanted CMOS Submicron Process • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)

SN74AHCT14

Abstract: schmitt-trigger hex inverter texas instruments
Contextual Info: SN74AHCT14 HEX SCHMITT-TRIGGER INVERTER S C L S 2 4 6 A -O C T O B E R 1995 - REVISED JA N U A R Y 1996 • Inputs Are TTL-Voltage Compatible • EP/C Enhanced-Performance Implanted CMOS Process • High Latch-Up Immunity Exceeds 300 mA Per JEDEC Standard JESD-17

HD-6440-9

Abstract: D-6440 HD-6440-2 HD-6101 HD-6435 HD-6436 HD-6440 HD-6495 HM-6100
Contextual Info: C M O S Bus D r iv e r F a m ily HD-6435 CMOS HEX RESETTABLE LATCHED BUS D R IVER T R U T H TA B LE F U N C T IO N A L D IA G R A M FEA TU R ES C O N T R O L IN PUTS Ri • S IN G L E POWER SU PP LY • H IG H N O IS E IM M U N IT Y • IN D U S T R IA L GRADES

Contextual Info: SN54AHC05, SN74AHC05 HEX INVERTERS WITH OPEN-DRAIN OUTPUTS S C LS 357D - MAY 1997 - R EVISED FEB R U A R Y 1999 • Operating Range 2-V to 5.5-V V c c • EPIC Enhanced-Performance Implanted CMOS Process • Latch-Up Performance Exceeds 250 mA Per JESD 17

AHCT14

Abstract: SN54AHCT14 SN74AHCT14
Contextual Info: SN54AHCT14, SN74AHCT14 HEX SCHMITT-TRIGGER INVERTERS S C L S 2 4 6 D -O C T O B E R 1 9 9 5 -R E V IS E D N O VEM BER 1996 Inputs Are TTL-Voltage Compatible • EPIC Enhanced-Performance Implanted CMOS Process • High Latch-Up Immunity Exceeds 250 mA

Contextual Info: SN54LVC06A, SN74LVC06A HEX INVERTER BUFFERS/DRIVERS WITH OPEN-DRAIN OUTPUTS S C A S 5 9 6 D -O C T O B E R 1 9 9 7 -R E V IS E D S E P TE M B E R 1998 • EPIC Enhanced-Performance Implanted CMOS Submicron Process • Inputs and Open-Drain Outputs Accept

prom 256x4 bit

Abstract: 6402 uart HD-6101 HD-6431 HD-6432 HD-6433 HD-6434 HM-6100 HM-6322 1024 x 4 prom
Contextual Info: C M O S B us D r iv e r F a m ily HD-6431 CMOS HEX LATCHING BUS DRIVER T R U T H TA B LE FU N C T IO N A L D IA G R A M FEATURES S IN G L E POWER SU PPLY H IG H N O ISE IM M U N IT Y IN D U S T R IA L G RADES AND D R IV E C A P A C IT Y M IL IT A R Y . . . .

SN54LVC14

Abstract: SN54LVC14A SN74LVC14A schmitt-trigger hex inverter texas instruments
Contextual Info: SN54LVC14A, SN74LVC14A HEX SCHMITT-TRIGGER INVERTER S C A S285F - MARCH 1993 - R EVISED AU G U S T 1997 EPIC Enhanced-Performance Implanted SN54LVC14A . . . J O R W PACKAGE SN74LVC14A . . . D, DB, OR PW PACKAGE (TOP VIEW CMOS) Submicron Process ESD Protection Exceeds 2000 V Per

prom 256x4 bit

Abstract: HB-61000 diode sy 171 hd receiver HD-6101 HD-6431 HD-6432 HD-6433 HD-6434 HM-6100
Contextual Info: C M O S B us D r iv e r F a m ily HD-6431 CMOS HEX LATCHING BUS D RIVER T R U T H TA B LE FU N C T IO N A L D IA G R A M FEATURES S IN G L E POWER SUPPLY H IG H N O ISE IM M U N IT Y IN D U S T R IA L G RADES AND D R IV E C A P A C IT Y M IL IT A R Y . . . .

LVC04A

Abstract: SN54LVC04A SN74LVC04A
Contextual Info: SN54LVC04A, SN74LVC04A HEX INVERTERS S C A S 2 8 1 H - JA N U A R Y 1 9 9 3 - R EVISED JU NE 1998 • EPIC Enhanced-Performance Implanted CMOS Submicron Process • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)

Contextual Info: SN54LV14A, SN74LV14A HEX SCHMITT-TRIGGER INVERTERS S C L S 3 8 6 B -S E P T E M B E R 1997 - R EVISED JU NE 1998 I • • EPIC Enhanced-Performance Implanted CMOS Process I I • Typical V q lp (Output Ground Bounce) < 0.8 V at VCc, Ta = 25°C I •

SN54AHCT174

Abstract: SN74AHCT174
Contextual Info: SN54AHCT174, SN74AHCT174 HEX D-TYPE FLIP-FLOPS WITH CLEAR S C L S 4 1 9 A -J U N E 1 9 9 8 - R EVISED S E P TE M B E R 1998 Inputs Are TTL-Voltage Compatible EP/C Enhanced-Performance Implanted CMOS Process Contain Six Flip-Flops With Single-Rail Outputs

SN54AHCT04

Abstract: SN74AHCT04
Contextual Info: SN54AHCT04, SN74AHCT04 HEX INVERTERS S C L S 2 3 2 D -O C T O B E R 1 9 9 5 -R E V IS E D N O VEM BER 1996 Inputs Are TTL-Voltage Compatible • EPIC Enhanced-Performance Implanted CMOS Process • High Latch-Up Immunity Exceeds 250 mA Per JEDEC Standard JESD-17

SN54AHCU04

Abstract: SN74AHCU04
Contextual Info: SN54AHCU04, SN74AHCU04 HEX INVERTERS S C LS 234D - O C TO B E R 1995 - R EVISED JU NE 1997 • Operating Range 2-V to 5.5-V Vc c • EPIC Enhanced-Performance Implanted CMOS Process • Unbuffered Outputs 1A [ 1 • High Latch-Up Immunity Exceeds 250 mA

Contextual Info: ACTS04MS fil H A R R IS S E M I C O N D U C T O R Radiation Hardened Hex Inverter December 1992 Features Pinouts • 1.25 Micron Radiation Hardened SOS CMOS • Total Dose Up To 1 Mega-RAD Si - Dose Rate Upset >1011 RAD(Si)/s 20ns Pulse- Cosmic Ray Upset Immunity (Typ. < 1 x 10'11 Errors/