HDLC MODEM Search Results

hdlc

Abstract: IEC3309 XF-HDLC RFC1619 XC4000XL HDLC controller CC318f
Contextual Info: HDLC Controller Solutions with Spartan-II FPGAs Customer Tutorial February 2000 File Number Here Agenda Introduction HDLC Overview HDLC Controller Applications Spartan-II IP Solutions for HDLC Controllers HDLC Controller ASSPs Spartan-II Family - Programmable ASSP

4ppm protocol

Abstract: CRC-16 CRC32 MC68160 MPC823 CRC-CCITT 0xFFFF 0XFFF0000 IrDA Protocol
Contextual Info: Communication Processor Module 16.9.18.5 SCC2 APPLETALK PROGRAMMING EXAMPLE. Except for the previously discussed register programming, use the example in Section 16.9.16.14 SCC2 HDLC Programming Example #1. 16.9.19 The SCC2 in Asynchronous HDLC Mode SCC2 Asynchronous HDLC is a frame-based protocol that uses HDLC framing techniques in

Bi-phase-L Coding

Abstract: CRC16 D555 MPC821 manchester differential
Contextual Info: Communication Processor Module 16.14 SERIAL COMMUNICATION CONTROLLERS The following is a list of the SCCs’ important features: • Implements HDLC/SDLC, HDLC bus, asynchronous HDLC, BISYNC, synchronous start/stop, asynchronous start/stop UART , AppleTalk/LocalTalk, and totally

MPC821

Contextual Info: Communication Processor Module 16.14.19.2 ASYNC HDLC CHANNEL FRAME TRANSMISSION PROCESSING. The ASYNC HDLC controller is designed to work with a minimum amount of intervention from the CPU core. It operates in a similar fashion to the HDLC controller on the MPC821.

Contextual Info: AM186CC Raw HDLC Driver CodeKit Embedded Processor Division V1.0 - Friday, July 24, 1998 Readme File : Version 1.1 - Friday, July 24, 1998 1 Overview This CodeKit contains a raw HDLC driver for the AMD AM186CC microprocessor. This is an interrupt driven HDLC driver that allows raw unformatted HDLC traffic to be transmitted and received. A small application is

TH21C

Abstract: TP31C hdlc 11-B DS3131 TD39
Contextual Info: DEMO KIT AVAILABLE DS3131 BoSS 40-Port, Unchannelized Bit-Synchronous HDLC www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS3131 bit-synchronous BoSS HDLC controller can handle up to 40 channels of highspeed, unchannelized, bit-synchronous HDLC. The on-board DMA has been optimized for

TP31C

Abstract: 083C Cables datasheet rh16c RH25CR hdlc 11-B DS3131 TD39 TH21C rbp2
Contextual Info: DEMO KIT AVAILABLE DS3131 BoSS 40-Port, Unchannelized Bit-Synchronous HDLC www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS3131 bit-synchronous BoSS HDLC controller can handle up to 40 channels of highspeed, unchannelized, bit-synchronous HDLC. The on-board DMA has been optimized for

testbench verilog ram 16 x 4

Abstract: HSCX 82525 hdlc R8051XC XC3S1500E-4 hscx82525
Contextual Info: LAPB/LAPD controlling machine providing − modulo 8 frame numbering HDLC − modulo 128 frame numbering HDLC Protocol Controller Core − automatically generated res- − one- or two-byte addressing ponses Serial Peripheral Interfaces − Bit stuffing The HDLC core implements a single- or dual-channel controller for the High-Level Data

PT7A6525

Abstract: PT7A6525J PT7A6525LJ PT7A6525L mc 6526 p pt7a6526je PT7A6525M PT7A6525LJE CD 1517 PT7A65
Contextual Info: Data Sheet PT7A6525/6525L/6526 HDLC Controller |

CD 40818 BE

Abstract: capacitor PMR 202 DM preset 103 CD4400 ARM7 ISA RW185 40818 SPC3 st c transistor 40410 CL-CD4400s
Contextual Info: CL-CD4400 'CIRRUSIDG/C Advance Data Book FEATURES • Four full-duplex, multi-protocol serial channels ■ All channels support async-HDLC/PPP, async, HDLC, or programmable sync ■ Sync bit rates up to 8 Mbits/sec. on all channels; up to 52 Mbits/sec. on a single channel in HDLC or

8273 dma controller

Abstract: Intel 8080 interface Intel 8080 CPU Diagram intel 8085 clock 8085 intel SDLC PROTOCOL intel 8273 8273
Contextual Info: in te 1 8273 PROGRAMMABLE HDLC/SDLC PROTOCOL CONTROLLER CCITT X.25 Compatible Programmable NRZI Encode/Decode HDLC/SDLC Compatible Two Programmable Modem Control Ports Full Duplex, Half Duplex, or Loop SDLC Operation Digital Phase Locked Loop Clock Recovery

8086 8257 DMA controller interfacing

Abstract: interfacing of 8257 with 8086 IC KD 2107 6 PIN 8257 DMA controller intel DMA controller Unit for 80186 8273 dma controller interfacing of 8257 devices with 8085 i8273
Contextual Info: in te i 8273 PROGRAMMABLE HDLC/SDLC PROTOCOL CONTROLLER CCITT X.25 Compatible Programmable NRZI Encode/Decode HDLC/SDLC Compatible Two Programmable Modem Control Ports Full Duplex, Half Duplex, or Loop SDLC Operation Digital Phase Locked Loop Clock Recovery

mc 6526 p

Abstract: PT7A6525 motorola 6526
Contextual Info: Data Sheet PT7A6525/6525L/6526 HDLC Controller |

8086 8257 DMA controller interfacing

Abstract: interfacing of 8257 with 8086 intel 8257 interrupt controller GA27-3093 Intel 8257 intel d 8273 intel 8273 8273 dma controller 8086 8257 DMA controller MCS-80
Contextual Info: in te i 8273 PROGRAMMABLE HDLC/SDLC PROTOCOL CONTROLLER CCITT X.25 Compatible Programmable NRZI Encode/Decode HDLC/SDLC Compatible Two Programmable Modem Control Ports Full Duplex, Half Duplex, or Loop SDLC Operation Digital Phase Locked Loop Clock Recovery

8086 8257 DMA controller interfacing

Abstract: interfacing of 8257 with 8086 8273 dma controller interfacing of 8257 devices with 8085 8086 8257 DMA controller intel 8257 intel 8080 architecture intel 8273 GA27-3093 8228 DI
Contextual Info: in t e i 8273, 8273-4, 8273-8 PROGRAMMABLE HDLC/SDLC PROTOCOL CONTROLLER • CCITT X.25 Compatible ■ Programmable NRZI Encode/Decode ■ HDLC/SDLC Compatible ■ Two User Programmable Modem Control Ports ■ Full Duplex, Half Duplex, or Loop SDLC Operation

Contextual Info: DALLAS SEMICONDUCTOR DS3131 Preliminary Data Sheet V2 January 26, 1999 DALLAS SEMICONDUCTOR DS3131 BoSS Bit Synchronous HDLC CONTROLLER 40 Port / 40 Channel HDLC Controller with Option for Local Bus Access Preliminary Data Sheet Version 2 January 26, 1999

TP31C

Abstract: DS3131 DS3134 LA10 LA12 TD39 811B
Contextual Info: DALLAS SEMICONDUCTOR DS3131 Preliminary Data Sheet V2 January 26, 1999 DALLAS SEMICONDUCTOR DS3131 BoSS Bit SynchronouS HDLC CONTROLLER 40 Port / 40 Channel HDLC Controller with Option for Local Bus Access Preliminary Data Sheet Version 2 January 26, 1999

HDLC verilog code

Abstract: testbench verilog ram 16 x 8 crc verilog code 16 bit VERILOG CODE FOR HDLC controller hdlc R8051XC verilog code of 16 bit comparator R8051XC-HDLC
Contextual Info:  LAPB/LAPD controlling machine providing  modulo 8 frame numbering HDLC  modulo 128 frame numbering HDLC Protocol Controller Core  automatically generated res-  one- or two-byte addressing ponses  Serial Peripheral Interfaces  Bit stuffing

HSCX 82525

Abstract: R8051XC-HDLC hdlc R8051XC
Contextual Info:  LAPB/LAPD controlling machine providing  modulo 8 frame numbering HDLC  modulo 128 frame numbering HDLC Protocol Controller Megafunction  automatically generated res-  one- or two-byte addressing ponses  Serial Peripheral Interfaces  Bit stuffing

TP31C

Abstract: r02f Boss NS-2 PAB1 td33 LDO DS3131 DS3134 LA10 LA12 TD39
Contextual Info: DALLAS SEM ICONDUCTOR DS3131 Preliminary Data Sheet V2 January 26, 1999 DALLAS SEMICONDUCTOR DS3131 BoSS Bit Synchronous HDLC CONTROLLER 40 Port / 40 Channel HDLC Controller with Option for Local Bus Access Preliminary Data Sheet Version 2 January 26, 1999

Contextual Info: DALLAS SEM ICONDUCTOR DS3131 Preliminary Data Sheet V1 August 6, 1998 DALLAS SEMICONDUCTOR DS3131 BOSS Bit and Octet Synchronous HDLC CONTROLLER 40 Port / 40 Channel HDLC Controller with Options for Local Bus Access & an Octet Synchronous Port Preliminary Data Sheet

RFC-1331

Abstract: CL-CD2431
Contextual Info: CL-CD2430ICD2431 DataBook 'CIRRUS LOGIC FEATURES • Four full-duplex multi-protocol channels, each running up to 128 kbits/second ■ Supports async, async-HDLC high-level data link control , and HDLC/SDLC (synchronous data link control) on all channels

TP31C

Abstract: PCI Backplane DS3131 DS3134 TC10 TC12 TD39 811af 32 bit pci backplane LD0-TC28
Contextual Info: DS3131 BoSS Bit SynchronouS HDLC Controller www.dalsemi.com FEATURES • • • • • • • • • • • 40 timing independent bit synchronous ports 40Rx & 40Tx coupled with 40 independent Bi-directional HDLC channels Each port can operate up to 52 Mbps

LA0-RD37

Contextual Info: PRELIMINARY DS3131 BoSS Bit SynchronouS HDLC Controller www.maxim-ic.com FEATURES § § § § § § 40 timing independent bit synchronous ports 40Rx and 40Tx coupled with 40 independent Bidirectional HDLC channels Each port can operate up to 52 Mbps 132Mbps full-duplex throughput