HD74L Search Results

Contextual Info: HD74LS390 Dual Decade Counters REJ03D0485-0400 Rev.4.00 May 10, 2006 This circuit contains eight master-slave flip-flops and additional gating to implement two individual four-bit counters. The HD74LS390 incorporates dual divide-by-two and divide-by-five counters, which can be used to implement cycle

Contextual Info: HD74LS165A Parallel-Load 8-bit Shift Register REJ03D0449–0300 Rev.3.00 Jul.15.2005 The LS165A are 8-bit serial shift registers that shift the data in the direction of QA toward QH when clocked. Parallel-in access to each stage is made available by eight individual direct data inputs that are enabled by a low level at the shift /

DIVIDE-BY-256

Abstract: ONU block diagram 74LSOO HD74LS393 a63a
Contextual Info: •D u a l 4-bit Binary Counters This circuit contains eight master-slave flip-flops and ad­ ditional gating to implement tw o individual four-bit counters. The HD74LS393 comprises tw o independent four-bit binary counters each having a clear and a clock input.

74LSOO

Abstract: HD74LS490
Contextual Info: HD74LS490. This c irc u it d itio n a l contains gating to eigh t master-slave im p le m e n t tw o Dual 4 -b it Decade Counters flip -flo p s ind ividu al 4 -b it and ad ­ I BLOCK DIAGRAM K decade counters. Each decade c o u n te r has ind ividu al clo ck, clear, and

74LSOO

Abstract: HD74LS367A kl66
Contextual Info: HD74LS367A * Hex Bus Drivers non-inverted data outputs with three-state outputs I PIN ARRANGEMENT I CIRCUIT SCHEMATIC D r i v e r se c tio n (1 / 6 ) C o n t r o l se c tio n Ootpu Control Ci ~ï7 ]vVcc — 1Output Cont roi Ci 'vLLKy L jc t-E I 6 " Y r]D *

74LSOO

Abstract: HD74LS374 HD74LSoop
Contextual Info: HD74LS374 • O c t a l D-type Edge-triggered Flip-Flops with th ree-state IP IN ARRANGEM ENT The H D74LS374, 8-bit registers features totem-pole threestate outputs designed specifically for driving highly-capacitive or relatively iow-impedance loads. The high-impedance third

74LSOOP

Abstract: 74LSOO
Contextual Info: HD74LS21 •D u al 4-input Positive AND Gates •PIN ARRANGEMENT ¡CIRCU IT SCHEMATICO^ ■ ELECTRICAL CH A RA CTERISTICS Item Symbol Input voltage VlL I6i IlH Input current IlL ¡1 Short-circuit output current Supply current Input clamp voltage * T est Conditions

DP 804 C

Abstract: JV3 diode 74LSOO HD74LS221
Contextual Info: HD74LS221 »Dual Monostable Multivibrators This multivibrator features a negative-transition-triggered input and a positive-transition-triggered input either of which can be used as an inhibit input. Pulse triggering occurs at a particular voltage level and is not directly related to the tran­

IS2074 diode

Abstract: flip flap 1S2074 400M HD74LS78A
Contextual Info: HD74LS78A Dual J-K Flip-Flops (with Preset. Common Clear, and Common Clock IBLOCK D IA G R A M ^ ) IP IN A R R A N G E M E N T •RECOMMENDED OPERATING CONDITIONS Ite m C lock fre q u e n c y Clock High w idth t* Preset r C le ar Sym bol fr t.r k Low min

1S2074

Abstract: HD74LS76A Hitachi Scans-001
Contextual Info: HD74LS76A. Dual J -K Flip-Flops w ith Preset and Clear IBLOCK D IA G R A M (12) IP IN A R R A N G E M E N T 7T| ix CK [ T PR "L 77] to PR CLR LR >-, Q Ö Lfi UE iDr 77] io 13 I CN 'cc ( T 77] 2K CK £7 ^ 77] 2Q 10 [ 2Q PR ~9~] 2J î, e (R E C O M M E N D E D OPERATING C O N D IT IO N S

HD74LVC16540

Abstract: Hitachi DSA00105
Contextual Info: HD74LVC16540 16-bit Buffers / Line Drivers with 3-state Outputs ADE-205-057B Z Rev.2 September 1995 Description The HD74LVC16540 has sixteen inverter drivers with three state outputs in a 48 pin package. When *1 and * 2 is low level, this drivers set up output is enable. Low voltage and high speed operation is

FP-14DA

Abstract: HD74LVC00 TTP-14D DSA003633
Contextual Info: HD74LVC00 Quad. 2-input NAND Gates ADE-205-060B Z Rev.2 September 1995 Description The HD74LVC00 has four 2-input NAND gates in a 14 pin package. Low voltage and high speed operation is suitable at the battery drive product (note type personal computer) and low power consumption extends

HD74LV373A

Abstract: DSA003634
Contextual Info: HD74LV373A Octal D-type Transparent Latches with 3-state Outputs ADE-205-274 Z 1st Edition April 1999 Description The HD74LV373A has eight D type latches with three state outputs in a 20 pin package. When the latch enables input is high, the Q outputs will follow the D inputs. When the latch enables goes low, data at the

HD74LV165A

Abstract: Hitachi DSA003732
Contextual Info: HD74LV165A Parallel-Load 8-bit Shift Register ADE-205-267 Z 1st Edition March 1999 Description The HD74LV165A is 8-bit serial shift register shifts data from QA to QH when clocked. Parallel inputs to each stage are enabled by a low level at the Shift/Load input. Also included is a gated clock input and a

HD74LV00A

Abstract: HD74LV2G00A DSA003634
Contextual Info: HD74LV2G00A Dual 2–input NAND Gates ADE-205-338A Z Rev.1 July 2001 Description The HD74LV2G00A has dual two–input NAND gates in a 8 pin package. Low voltage and high speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power

HD74LV2G34A

Abstract: DSA003635
Contextual Info: HD74LV2G34A Triple Noninverters ADE-205-345B Z Rev.2 July 2001 Description The HD74LV2G34A has triple noninverters in a 8 pin package. Low voltage and high speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power consumption

FP-14DA

Abstract: FP-14DN HD74LVU04A TTP-14D DSA003634
Contextual Info: HD74LVU04A Hex Inverters ADE-205-248 Z 1st Edition March 1999 Description The HD74LVU04A has six inverters with unbuffered outputs in a 14-pin package. Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the low-power consumption extends the battery life.

HD74LVC240A

Abstract: DSA003634
Contextual Info: HD74LVC240A Octal Buffers / Line Drivers with 3-state Outputs ADE-205-109B Z 3rd Edition December 1996 Description The HD74LVC240A has eight inverter drivers with three state outputs in a 20 pin package. This device is a inverting buffer and has two active low enables (1G and 2G). Each enable independently controls four

TM 1628 IC

Abstract: FP-14DA FP-14DN HD74LV21A TTP-14D DSA003634
Contextual Info: HD74LV21A Dual 4-input Positive AND Gates ADE-205-255 Z 1st Edition March 1999 Description The HD74LV21A performs the Boolean functions Y = A•B•C•D or Y = A+B+C+D in positive logic. Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook

HD74LV574A

Abstract: DSA003634
Contextual Info: HD74LV574A Octal Edge-Triggered D-type Flip-Flops with 3-state Outputs ADE-205-280 Z 1st Edition April 1999 Description The HD74LV574A has eight edge-triggered D-type flip-flops with three-state outputs in a 20-pin package. Data at the D inputs meeting set up requirements, are transferred to the Q outputs on positive going

HD74LV2GU04A

Abstract: HD74LVU04A DSA003634
Contextual Info: HD74LV2GU04A Triple Unbuffered Inverters ADE-205-341A Z Rev.1 July 2001 Description The HD74LV2GU04A has triple unbuffered inverters in a 8 pin package. Low voltage and high speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power

Hitachi DSA003767

Abstract: HD74LVC373A
Contextual Info: HD74LVC373A Octal D-type Transparent Latches with 3-state Outputs ADE-205-112B Z 3rd Edition December 1996 Description The HD74LVC373A has eight D type latches with three state outputs in a 20 pin package. When the latch enable input is high, the Q outputs will follow the D inputs. When the latch enable goes low, data at the D

HD74LVC16374A

Abstract: Hitachi DSA003765
Contextual Info: HD74LVC16374A 16-bit D-type Flip Flops with 3-state Outputs ADE-205-122B Z 3rd Edition December 1996 Description The HD74LVC16374A has sixteen edge trigger D type flip flops with three state outputs in a 48 pin package. Data at the D inputs meeting set up reguirements, are transferred to the Q outputs on positive

HD74LVCZ244A

Abstract: DSA003634
Contextual Info: HD74LVCZ244A Octal Buffers / Line Drivers with 3–state Outputs ADE-205-230A Z 2nd. Edition February 1999 Description The HD74LVCZ244A has eight line drivers with three state outputs in a 20 pin package. This device is a noninverting buffer and has two active low enables (1G and 2G). Each enable independently controls four