HD74HC27 Search Results

HD74HC27

Abstract: Hitachi DSA0095 DP-14 FP-14DA FP-14DN
Contextual Info: HD74HC27 Triple 3-input NOR Gates ADE-205-415 Z 1st. Edition Sep. 2000 Features • • • • • High Speed Operation: tpd = 10 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max

HD74HC279

Abstract: HD74HC279FPEL PRSP0016DG-A PRSP0016DH-B
Contextual Info: HD74HC279 Octal D-type Flip-Flops with Clear REJ03D0605–0200 (Previous ADE-205-483) Rev.2.00 Jan 31, 2006 Description The latch is ideally suited for use as temporary stage for binary information processing and input/output units. When either S or R is low, output is dependent on R input. When both inputs are high, Output is stored before the indicated

Contextual Info: HD74HC273 Octal D-type Flip-Flops with Clear This device contains 8 master-slave flip-flops with a common | PIN ARRANGEMENT clock and common clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The clear

HD74HC273P

Contextual Info: HD74HC273 Octal D-type Flip-Flops with Clear REJ03D0604-0200 Rev.2.00 Nov 04, 2008 Description This device contains 8 master-slave flip-flops with a common clock and common clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The clear

Hitachi DSA00279

Contextual Info: HD74HC27 Triple 3-input NOR Gates Features • • • • • High Speed Operation: tpd = 10 ns typ CL = 50 pF High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 1 µA max (Ta = 25°C)

Contextual Info: HD74HC27 # Triple 3-input NOR Gates • FEATURES I • High Speed O peration: tp rf“ 10n» ty p . Q _” 50pF • High O u tp u t C urrent: Fanout o f 10 L S T T L Load« • Wide O perating Voltage: Vcc” 2 ~ 6V • Low In p u t C urrent: 1>iA max. • L o w Q uietcent Supply C urrent: icc (static) ■■1mA max. (T « « 2 5 “ C)

Contextual Info: HD74HC27 • Triple 3-input NOR Gates • FEATURES I PIN ARR ANG E M E NT • High Speed Operation: tpc/= 10ns ty p . C/_ = 50 p F Vcc • High O u tp u t Current: Fanout of 10 L S T T L Loads 1C • Wide Operating Voltage: l/'cc = 2 ~ 6 V • Low In put C urrent: 1/iA max.

74hc273

Contextual Info: HD74HC273 # Octal D-type Flip-Flops with Clear This device contains 8 master-slave flip-flops with a common | PIN ARRANGEMENT clock and common clear. Data on the D input having the “W specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The clear

HD74HC279

Abstract: DSA003717 Hitachi DSA003717
Contextual Info: HD74HC279 Quad. S–R Latches Description The latch is ideally suited for use as temporary stage for binary information processing and input/output units. When either S or R is low, output is dependent on R input. When both inputs are high, Output is stored before the indicated steady-state input conditions were established. And when both inputs are low,

HD74HC27

Abstract: HD74HC27FPEL HD74HC27P PRDP0014AB-B PRSP0014DF-B
Contextual Info: HD74HC27 Triple 3-input NOR Gates REJ03D0543-0200 Previous ADE-205-415 Rev.2.00 Oct 06, 2005 Features • • • • • • High Speed Operation: tpd = 10 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V

HD74HC273

Abstract: Hitachi DSA00389
Contextual Info: HD74HC273 Octal D-type Flip-Flops with Clear Description This device contains 8 master-slave flip-flops with a common clock and common clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition

Contextual Info: HD74HC279 # Quad. S —R Latches PIN ARRANGEMENT The latch is ideally suited for use as tem porary stage for binary information processing and input/output units.W hen either S or R is low , output is dependent on R input. W hen both inputs are high, O utput is stored before the indicated steadystate input conditions were established. A nd w hen both

Contextual Info: HD74HC27 % Triple 3-input NOR Gates • FEATURES • • • • • I PIN ARRANGEMENT High Speed Operation: tp^=10ns typ. Cf»50pF High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: Vcc~2 ~ 6 V Low Input Current: 1*tA max. Low Quiescent Supply Current: Icc (static) ■ 1mA max. (ra«2 6 °C )

Contextual Info: HITACHI/ LOGIC/ARRAYS/NEM HE HD74HC273 # DËJ 44Tb2Q3 QQIQHTt. Octal D-type Flip-Flops with Clear 92D This device contains 8 master-slave flip-flops with a common d o c k and common clear. Data on the D input having the | 10476 D T -4 6 -0 7 -1 1 PIN ARRANGEMENT

DP-14

Abstract: FP-14DA FP-14DN HD74HC27 Hitachi DSA00386
Contextual Info: HD74HC27 Triple 3-input NOR Gates Features • • • • • High Speed Operation: tpd = 10 ns typ CL = 50 pF High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 1 µA max (Ta = 25°C)

HD74HC273P

Abstract: HD74HC273RPEL HD74HC273 HD74HC273TELL HD74HC273FPEL PRDP0020AC-B PRSP0020DD-B TSSOP-20
Contextual Info: HD74HC273 Octal D-type Flip-Flops with Clear REJ03D0604-0300 Rev.3.00 Mar 25, 2009 Description This device contains 8 master-slave flip-flops with a common clock and common clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The clear

HD74HC273

Abstract: Hitachi DSA00222
Contextual Info: HD74HC273 Octal D-type Flip-Flops with Clear ADE-205-482 (Z) 1st. Edition Sep. 2000 Description This device contains 8 master-slave flip-flops with a common clock and common clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition

HD74HC279

Abstract: Hitachi DSA00222
Contextual Info: HD74HC279 Quad. S–R Latches ADE-205-483 Z 1st. Edition Sep. 2000 Description The latch is ideally suited for use as temporary stage for binary information processing and input/output units. When either S or R is low, output is dependent on R input. When both inputs are high, Output is

Contextual Info: HITACHI/ LOGIC/ARRAYS/MEM T5 0G1G334 92D HD74HC27 # 10334 d fl J ~ T '^ 3 " 2 -/ Triple 3-input NOR Gates • FEATURES • High Speed Operation: 10ns typ. Ci.«50pF • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: l/c c * 2 ~ 6 V

Contextual Info: HD74HC279 Quad. S —R Latches The Latch is ideally suited for use as temporary stage for binary Information processing and input/output units.W hen either S or R is low , output is dependent on R input. W hen both inputs are high. Output is stored before the indicated steadystate input conditions were established. And when both

Contextual Info: HD74HC279 # Quad. S - R Latches PIN ARRANGEMENT The latch is ideally suited for use as temporary stage for binary information processing and input/output units.When either S or R is low, output is dependent on R input. When both inputs are high. Output is stored before the indicated steadystate input conditions were established. And when both

HD74HC273

Contextual Info: HD74HC273 Octal D-type Flip-Flops with Clear This device contains 8 matter-slave flip-flops »with a common dock and common clear. Oats on the D input having the | PIN ARRANGEMENT specified setup and hold times is transferred to the Q output on the low to high transition of the d ock input. The clear

Contextual Info: To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid

HD74HC273P

Abstract: HD74HC273 HD74HC273FPEL HD74HC273RPEL HD74HC273TELL PRDP0020AC-B PRSP0020DD-B TSSOP-20
Contextual Info: To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid