HD74AL Search Results

Hitachi DSA0095

Abstract: 1B10 1B12 HD74ALVCH16269
Contextual Info: HD74ALVCH16269 12-bit to 24-bit Registered Bus Transceivers with 3-state Outputs ADE-205-136 Z Preliminary 1st. Edition May 1996 Description The HD74ALVCH16269 is used in applications where two separate ports must be multiplexed onto, or demultiplexed from, a single port. The device is particularly suitable as an interface between

Hitachi DSA00104

Abstract: HD74ALVC162831
Contextual Info: HD74ALVC162831 1-bit 4-bit Address Register / Driver with 3-state Outputs ADE-205-200 Z Preliminary 1st. Edition November 1997 Description This 1-bit to 4-bit address register / driver is designed for 2.3 V to 3.6 V VCC operation. The device is ideal for use in applications in which a single address bus is driving four separate memory locations. The

2Y16

Abstract: 1y14 Hitachi DSA00104 HD74ALVC16830 2Y14
Contextual Info: HD74ALVC16830 1-bit to 2-bit Address Driver with 3-state Outputs ADE-205-198 Z Preliminary 1st. Edition November 1997 Description This 1-bit to 2-bit address driver is designed for 2.3 V to 3.6 V VCC operation. To ensure the high impedance state during power up or power down, the output ebable ( ) input should be tied to VCC

Contextual Info: HD74ALVC16834 18-bit Universal Bus Driver with 3-state Outputs and Inverted Latch Enable HITACHI ADE-205-216C Z Preliminary, 4th. Edition Jan. 1, 1999 Description The HD74ALVC16834 is an 18-bit universal bus driver designed for 2.3 V to 3.6 V Vcc operation.

Hitachi DSA0098

Abstract: 1B10 1B12 HD74ALVCHR162269
Contextual Info: HD74ALVCHR162269 12-bit to 24-bit Registered Bus Exchanger with 3-state Outputs ADE-205-190 Z Preliminary, 1st. Edition February 1997 Description The HD74ALVCHR162269 is a 12-bit to 24-bit registered bus exchanger, which is intended for applications where two separate ports must be multiplexed onto, or demultiplexed from, a single port. It is

Hitachi DSA0095

Abstract: HD74ALVCH16501
Contextual Info: HD74ALVCH16501 18-bit Universal Bus Transceivers with 3-state Outputs ADE-205-168A Z 2nd. Edition December 1999 Description Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A to B data flow, the device operates in the

HD74ALVCF162835

Abstract: Hitachi DSA00115
Contextual Info: HD74ALVCF162835 18-bit Universal Bus Driver with 3-state Outputs ADE-205-227E Z Preliminary, 6th. Edition Feb. 1, 1999 Description The HD74ALVCF162835 is an 18-bit universal bus driver designed for 2.3 V to 3.6 V VCC operation. Data flow from A to Y is controlled by the output enable (OE). The device operates in the transparent mode

HD74ALVCH16836

Abstract: Hitachi DSA00115
Contextual Info: HD74ALVCH16836 20-bit Universal Bus Driver with 3-state Outputs ADE-205-213 Z Preliminary, 1st. Edition January 1998 Description This 20-bit universal bus driver is designed for 2.3 V to 3.6 V VCC operation. Data flow from A to Y is controlled by the output enable (O E) input. The device operates in the

1B12

Abstract: HD74ALVCH16260 DSA003634
Contextual Info: HD74ALVCH16260 12-bit to 24-bit Multiplexed D-type Latches with 3-state Outputs ADE-205-135B Z 3rd. Edition December 1999 Description The HD74ALVCH16260 is a 12-bit to 24-bit multiplexed D-type latch used in applications where two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. Typical

HD74ALVC1G00

Abstract: DSA003635
Contextual Info: HD74ALVC1G00 2–input NAND Gate ADE-205-604C Z Rev.3 Aug. 2001 Description The HD74ALVC1G00 has two–input NAND gate in a 5 pin package. Low voltage and high speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power

HD74ALVCH162831

Abstract: DSA003634
Contextual Info: HD74ALVCH162831 1-bit 4-bit Address Register / Driver with 3-state Outputs ADE-205-195 Z Preliminary 1st. Edition March 1998 Description This 1-bit to 4-bit address register / driver is designed for 2.3 V to 3.6 V VCC operation. The device is ideal for use in applications in which a single address bus is driving four separate memory locations. The

HD74ALVC2G06

Abstract: DSA003635
Contextual Info: HD74ALVC2G06 Triple Inverter Buffers / Drivers with Open Drain ADE-205-632A Z Rev. 1 August. 2001 Description The HD74ALVC2G06 has triple inverter buffers / drivers with open drain outputs in a 8 pin package. Low voltage and high speed operation is suitable for the battery powered products (e.g., notebook computers),

HD74ALVCH16374

Abstract: DSA003634
Contextual Info: HD74ALVCH16374 16-bit D-type Flip Flops with 3-state Outputs ADE-205-123B Z 3rd. Edition December 1999 Description The HD74ALVCH16374 has sixteen edge trigger D type flip flops with three state outputs in a 48 pin package. Data at the D inputs meeting set up requirements, are transferred to the Q outputs on positive

Contextual Info: HD74ALVCH162500 18-bit Universal Bus Transceivers with 3-state Outputs HITACHI ADE-205-181 Z Preliminary, 1st. Edition December 1996 Description Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A to B data flow, the device operates in the

Contextual Info: HD74ALVCH16721 3.3-V 20-bit Flip Flops with 3-state Outputs HITACHI ADE-205-139 Z Preliminary 1st. Edition May 1996 Description The HD74ALVCH1672rs twenty flip flops are edge triggered D-type flip flops with qualified clock storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs,

Contextual Info: HD74ALVCH16373 16-bit Transparent D-type Latches with 3-state Outputs HITACHI ADE-205-138 Z Preliminary 1st. Edition May 1996 Description The HD74ALVCH16373 is particularly suitable for implementing buffer registers, I/O ports, bi-directional bus drivers, and working registers. It can be used as two 8-bit latches or one 16-bit latch. When the latch

Contextual Info: HD74ALVCH16827 20-bit Buffers / Drivers with 3-state Outputs HITACHI ADE-205-140A Z 2nd. Edition September 1997 Description The HD74ALVCH16827 is composed of two 10-bit sections with separated output enable signals. For either 10-bit buffer section, the two output enable (lO E l and 10E 2 or 20E 1 and 20E 2) inputs must both

Contextual Info: HD74ALVCH16721 3.3-V 20-bit Flip Flops with 3-state Outputs HITACHI ADE-205-139A Z 2nd. Edition September 1997 Description The HD74ALVCH16721’s twenty flip flops are edge triggered D-type flip flops with qualified clock storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q

Contextual Info: HD74ALV CH162373 16-bit Transparent D-type Latches with 3-state Outputs HITACHI ADE-205-179 Z Preliminary, 1st. Edition December 1996 Description The HD74ALVCH162373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as two 8-bit latches or one 16-bit latch. When the latch

Contextual Info: HD74ALVCH16374 16-bit D-type Flip Flops with 3-state Outputs HITACHI A D E - 2 0 5 - 1 2 3 Z Preliminary, Rev.O October 1995 Description The HD74ALVCH16374 has sixteen edge trigger D type flip flops with three state outputs in a 48 pin package. Data at the D inputs meeting set up requirements, are transferred to the Q outputs on positive

Contextual Info: HD74ALVCH16260 12-bit to 24-bit Multiplexed D-type Latches with 3-state Outputs HITACHI ADE-205-135A Z 2nd. Edition September 1997 Description The HD74ALVCH16260 is a 12-bit to 24-bit multiplexed D-type latch used in applications where two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. Typical

Contextual Info: HD74ALVCH162721 3.3-V 20-bit Flip Flops with 3-state Outputs HITACHI ADE-205-184A Z 2nd. Edition September 1997 Description The HD74ALVCH16272rs twenty flip flops are edge triggered D-type flip flops with qualified clock storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs,

Contextual Info: HI T A C H I / LOGIC/ARRAYS/MEfl Sfl DÈI 4 4 ^ 2 0 3 0005541 T 58C 05241 HD74ALS03 •Quadruple 2 -input Positive NAND Gates with open collector outputs ~p L Lf IPIN ARRANGEMENT P" I *B (T op V iew ) •ELECTRICAL CHARACTERISTICS (Ta - 20— 1-75‘C)

sfl28

Contextual Info: HD74ALVCH16269 12-bit to 24-bit Registered Bus Transceivers with 3-state Outputs HITACHI ADE-205-136 Z Preliminary 1st. Edition May 1996 Description The HD74ALVCH16269 is used in applications where two separate ports must be multiplexed onto, or demultiplexed from, a single port. The device is particularly suitable as an interface between synchronous