HD494 Search Results

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Abstract: 64 QAM modulator demodulator HD49429F uncorrectable errors FEC soft 256qam HD49430F PQFP-100 equalizer algorithm multipath qam circuit CLK10M
Contextual Info: HD49430F Preliminary Specification Rev. 2 April 1, 1998 General Description HD49430F is a highly integrated Downstream Processor optimized for applications such as Cable Modems and Set-top boxes and forms a complete and optimal solution with its companion HD49429F Upstream

SAS3

Abstract: HD494 picture-in-picture motion interpolation HM63021P
Contextual Info: HD49406 -Memory Controller Description The HD49406 controls HM53051P frame memory and HM63021P line memory. It also distributes pulses to YSP, INT, and CSP. Functions • Frame memory control: generates HM53051P signals CGW, CGR, SAD, SAS, TAS, WE, and

Contextual Info: ADE-XXX-XXX HD49410FS PIP Controller PAL Suited (with Built-In A/D, D/a Converters) Rev. 2 Sep. 1993 The HD49410FS is a memory controller for PAL suited PIP (picture - i n - p i c t u re) systems and incorporates a 1-channel 6-bit A/D converter, a 2channel 6-bit D/A conve rt e r, a 3-ch a n n e l

HD49420

Contextual Info: HD49420FS-PIP Controller for NTSC with On-Chip A/D and D/A Converters Description T h e H D 4 9 4 2 0 F S is a m e m o r y c o n t r o l l e r f o r N T S C -type picture-in-picture (PIP) systems. The chip integrates one 6-bit A /D converter, tw o 7-bit

Contextual Info: HD49409FS P-in-P C o n tro ller w ith Built-in A/D, D /A C onverters Description Features The H D 49 409 F S is a m em ory controller for P-in-P (p ic tu re -in -p ic tu re ) system s and in co rp o ra te s a 1-channel 6-bit A/D converter, a 2-channel 8-bit

Contextual Info: HD49429F PRELIMINARY SPECIFICATION HITACHI Preliminary Specification March 1998 Description HD49429F is a highly integrated MCNS compliant Upstream processor optimized for applications such as Cable Modems and Set-top boxes. It forms a complete and optimal solution with its companion

Contextual Info: HD49430F Preliminary Specification HITACHI Rev. 2 April 1, 1998 General Description HD49430F is a highly integrated Downstream Processor optimized for applications such as Cable Modems and Set-top boxes and forms a complete and optimal solution with its companion HD49429F Upstream

Contextual Info: HD49428F QAM Cable Demodulator HITACHI November 1996 Description The HD49428F is a complete 256/64 QAM demodulator implementation suitable for use in Cable set-top applications. It can operate in systems using symbol rates up to 5.5 Mbauds. The HD49428F uses a fully digital state of the art QAM Demodulator architecture which combines high

QAM16

Abstract: HD494 hd49430
Contextual Info: HD49429F Preliminary Specification HITACHI Rev. 2 March 2, 1998 General Description HD49429F is a highly integrated MCNS compliant Upstream processor optimized for applications such as Cable Modems and Set-top boxes. It forms a complete and optimal solution with its companion HD49430F

ha11569

Abstract: ha1156
Contextual Info: HD49412FS PIP Controller NTSC Suited (with Built-In A/D, D/A Converters) T he H D 49412FS is a m em ory controller for N TSC s u it e d P IP ( p i c t u r e - i n - p i c t u r e ) s y s te m s a n d incorporates a 1-channel 6-bit A /D converter, a 2c h a n n e l 6 - b it D /A c o n v e r te r , a 3 - c h a n n e l

A118088

Abstract: HM53461/HM53462
Contextual Info: HD4941OFS PIP Controller PAL Suited (with Built-In A/D, D/A Converters) The HD49410FS is a memory controller for PAL suited PIP (p ictu re-in -p ictu re) system s and incorporates a 1-channel 6-bit A/D converter, a 2channel 6-bit D /A converter, a 3-channel

ha118

Abstract: ha11808
Contextual Info: HD49409FS-PIP Controller with Built-In A/D, D/A Converters The HD49409FS is a memory controller for PIP (picture-in-picture) systems and incorporates a 1channel 6-bit A/D converter, a 2-channel 8-bit D/A converter, a 3-channel multiplexer, a 4 fsc PLL

HD4942

Abstract: qam circuit
Contextual Info: HD49430F Preliminary Specification HITACHI Rev. 2 April 1, 1998 General Description HD49430F is a highly integrated Downstream Processor optimized for applications such as Cable Modems and Set-top boxes and forms a complete and optimal solution with its companion HD49429F Upstream

Contextual Info: HD49404 Luminance Signal Processor Functions • • • • Motion adaptive Y/C separation Motion detection Edge detection Noise reduction Features • Separates Y signal based on amount of motion using the following filters: — Still picture: Frame comb filter

HD4942

Contextual Info: Preliminary HD49421FS PIP Controller for NTSC with On-Chip A/D and D/A Converters Description Features T he H D 4 9 4 2 1 F S is a m em ory co n tr o lle r for NTSC -type picture-in-picture (PIP) system s. The chip integrates one 6-bit A /D converter, two 7-bit

HD49429F

Abstract: SDA 5450 randomizer 15-bit HD49430F HD4942 fifo buffer ram 512 byte 56F640
Contextual Info: HD49429F Preliminary Specification Rev. 2 March 2, 1998 General Description HD49429F is a highly integrated MCNS compliant Upstream processor optimized for applications such as Cable Modems and Set-top boxes. It forms a complete and optimal solution with its companion HD49430F

HD494

Contextual Info: HD49428F QAM Cable Demodulator HITACHI November 1996 Description The HD49428F is a complete 256/64 QAM demodulator implementation suitable for use in Cable set-top applications. It can operate in systems using symbol rates up to 5.5 Mbauds. The HD49428F uses a fully digital state of the ait QAM Demodulator architecture which combines high

picture-in-picture motion interpolation

Contextual Info: HD49405 Scanning Line Interpolator Functions • Motion adaptive scan line interpolation • Tw o-dim ensional enhancer: horizontal and vertical enhancement adjusted independently • Motion time-space filter Features • Internal scan line interpolation based on amount

Contextual Info: HD49420FS PIP Controller for NTSC with On-Chip A/D and D/A Converters Description Features The HD49420FS is a memory controller for NTSC-type picture-in-picture (PIP) systems. The chip integrates one 6-bit A/D converter, two 7-bit D/A converters, a three-channel multiplexer, a 4fSC

Contextual Info: ADE-XXX-XXX HD49409FS PIP Controller with Built-in A/D, D/A Converter Rev. 0 Aug. 1990 The HD49409FS is a memory controller for PIP (picture-in-picture) systems and incorporates a 1channel 6-bit A/D converter, a 2-channel 8-bit D/A conve rt e r, a 3-channel multiplexer, a 4 f sc PLL

Contextual Info: HD49409FS P-in-P Controller with Built-in A/D, D/A Converters Description Features T h e H D 4 9 4 0 9 F S is a m e m o ry c o n tro lle r for P -in -P ( p ic tu re - in -p ic tu r e ) s y s te m s a n d in c o r p o ra te s a 1-ch an n el 6 -b it A /D co n v erter, a 2 -ch an n el 8-bit

ha118088

Abstract: IC for 2Channel to 5.1 converter circuit diagram A575 HA1152 HD49409FS HD494
Contextual Info: HD49409FS P -in -P C o n tro lle r w ith B u ilt-in A /D , D /A C o n v e rte rs Description Features T he H D 49409FS is a m em ory controller for P-in-P (p ictu re-in -p ictu re) system s and in co rp o rates a 1-channel 6-bit A /D converter, a 2-channel 8-bit

Q223

Abstract: ha11569fs
Contextual Info: ADE-XXX-XXX HA11569FS PIP Chroma H/V Signal Processing LSI NTSC Rev. 2 Sep 1993 The HA11569FS is a main/sub Picture chroma and H/V signal processing LSI with built-in video sw i t ch for NTSC suited PIP systems. Th e HA11569FS implements on a single chip the PIP

Contextual Info: MITSUBISHI ICs TV M50571FP SYNC SIGNAL PROCESSING DESCRIPTION The M50571FP is a semiconductor integrated circuit for generating various sync signals and clock signals for EDTV system. A specially designed standard signal/non-standard signal detecting circuit also responds to non-standard signals. It