HALO TG 110 Search Results

TG110-ESV01N6

Abstract: HALO TG110-ESV01N6 0130-M halo tg 110
Contextual Info: US PATENT NO. 5.656,985 6.297.720B1 6,297.721 B1 6.320.489B1 6.344.785B1 PART NO. : TG110-ESV01N6 0.580 max • [14.73] - 16PIN SOIC FOOTPRINT ISOLATION/IMPEDANCE MATCHING AND CMR CHOKE MODULE UL60950 RECOGNIZED ENHANCED SHOCK/VIBRATION PERFORMANCE EXTENDED OPERATING TEMPERATURE -4 0 / + 8 5 *C

720B1

Abstract: TG110-E470NXRL 2s772 TG110
Contextual Info: US PAIENT N a M S M » W S7.720B1 I.2S7.721B1 8,320.W « 1 6,344,78581 8.M 2,431 B l PART NO. : TG110-E470NXRL 1.100 max [27.94] FOUR-PORT 10/10OBASE—TX ISOLATION MODULE nnHRnnHRnnRRnnnnnHRn- HALO RoHS COMPLIANT Quatra TG110 -E 4 7 0 N X HI POTTED COMPATIBLE TO LEAD-FREE SOLDERING PROCESS

T7032

Abstract: XT907 AIKS ST7032 driver pe-65994 23Z90 LXT907 23Z128 pulse 23z128 SM23Z90
Contextual Info: Preliminary Information March 1994 LXT907 , Ethernet Interface for Hub Switch and Adapter Applications Internal MAU with Integrated W Base T MAU, En Dec, A U I and Filters The LXT907 Ethernet Interface is designed for IEEE 802.3 physical layer Hub/Switch and Adapter applications. It

ST7032 driver

Abstract: PT4069 PM6044 LXT907 S553-0716
Contextual Info: APRIL, 1996 DATA SHEET LXT907 Universal Ethernet Interface Adapter Internal MAU with Integrated 10BASE-T MAU, EnDec, AUI and Filters Generai Description The LXT907 Universal Ethernet Interface Adapter is de­ signed for IE E E 802.3 physical layer applications. It pro­

ST7011

Abstract: VALOR pt4069 PT4069 Valor Electronics PM6044 FIL-MAG* 23Z90 LT6030 st7030 MB86950 10BASE-TMAU m-tron mp-1
Contextual Info: APRIL 1996 LXT901 Universal Ethernet Interface Adapter Internal MAU with Integrated 10BASE-T MAU, EnDec, AU I and Filters General :eatures The LXT901 Universal Ethernet Interface Adapter is de­ signed for IEEE 802.3 physical layer applications. It pro­

MSC1311-01B

Contextual Info: PTEMBER 1998 Revision 1.0 LXT310 T1 CSU/ISDN PRI Transceiver The LXT310 is the First fully integrated transceiver for T l CSU and ISDN Primary Rate Interface ISDN PRI applications at 1.544 Mbps. This transceiver operates over 6,000 feet of 22 AWG twisted-pair cable without any

Contextual Info: HB56A240 Series 2,097,152-Word x 40-Bit High Density Dynamic RAM Module • PINOUT ■ DESCRIPTION The HB56A240B/SB is a 2M x 40 dynamic RAM module, mounted 20 pieces of 4 Mbit DRAM HM514400AS sealed in SOJ package. An outline of the HB56A240B/SB is a 72-pin single in-line package. Therefore, the HB56A240B/

Contextual Info: HM5116400 Series 4,194,304-Word x 4-Bit 4 4 cib2Q3 o o i a a ^ a SIE » H T - ^ 2 3 - 19 4?a « h i t e Product Preview H I TA C H I / L O G I C / A R R A Y S / M E M Dynamic Random Access Memory • DESCRIPTION HM5116400J Series The Hitachi HM5116400 is a CMOS dynamic RAM organized 4,194,304 words x

Contextual Info: HITACHI/ LOGIC/ARRAYS/MEM 51E D MM 1 b 5Q 3 OOlflS?«? fl73 • H I T S HM514400A Series HM514400AL Series Low P ow er Version HM514400ASL Series Super Low Pow er Version Preliminary 1,048,576-Word x 4-Bit Dynamic Random Access Memory HM514400AJ/AU/ALSJ Series

ND R304.3

Abstract: ND R315 TP218 transistor DIODE S4 2G TP218 IC TP246 transistor transmitter module R315 MDIO communication protocol TP218 100BASE-FX
Contextual Info: LXD974A Demo Board for 10/100 Applications Development Kit Manual January 2001 As of January 15, 2001, this document replaces the Level One document LXD974A Demo Board for 10/100 Applications. Order Number: 249104-001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual

AL 901A

Contextual Info: DA TA S H E E T MARCH 1998 Revision 1.2 LXT901A/907A Universal Ethernet Transceiver G eneral Description Features The LX T901A and LX T 907A Universal Ethernet Transceivers are new-generation LXT901 and LXT907 replacements with improved noise immunity and output

TP218 IC

Abstract: ABT24 R290 lwd52 R353 c174 TG110-S462NX S462N R289 TP218
Contextual Info: USER GUIDE SEPTEMBER 1998 Revision 2.0 LXD975A for 10/100 Applications General Description Features • Four independent IEEE 802.3-compliant 10BASE-T or 100BASE-TX ports. The LXD975A Demo Board is a four-port 10/100 Mbps Ethernet Media Access Unit MAU that demonstrates all

7011s

Abstract: BA 5977
Contextual Info: DATA SHEET APRIL 1997 LXT944 Revision 2.0 Quad Ethernet Interface Adapter The L X T944 is the first quad lO BA SE-T transceiver device w ith integrated filters. T he L X T944 Q uad E thernet A dapter is designed for IEEE 802.3 physical layer applica­ tions. T his single CM O S device includes all o f the active

Contextual Info: C S 61584A A dvanced Product D ata bo ok — CIRRUS LOGIC FEATURES • Dual T1/E1 Line Interface ■ 3.3 Volt and 5 Volt Versions ■ Crystal less Jitter Attenuator Meets European CTR 12 and ETSI ETS 300 011 Specifications ■ Matched Impedance Transmit Drivers

Contextual Info: PR E LIM IN A R Y a Am79C961 Advanced Micro Devices PCnet -ISA+Jumperless Single-Chip Ethernet Controller for ISA DISTINCTIVE CHARACTERISTICS • Single-chip Ethernet controller for the Industry Standard Architecture ISA and Extended Industry Standard Architecture (EISA) buses

DP83924A

Contextual Info: National Semiconductor October 1997 DP83924A Quad 10 Mb/s Ethernet Transceiver General Description Features The Quad 10 Mb/s Ethernet Transceiver is a 4-Port Encoder/Decoder ENDEC that includes all the circuitry required to interface four Ethernet Media Access Control­

Contextual Info: P R ELIM IN A R Y Am79C961 PCnet -ISA+Jumperless Single-Chip Ethernet Controller for ISA Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • Single-chip Ethernet controller for the Industry Standard Architecture ISA and Extended Industry Standard Architecture (EISA) buses

CSR86

Abstract: FL1043 valor fl1043 diagram of bp 1361 led driver sa1015 PQJ120 CSR30-31 CSR94 VIP 22A led driver DCU0-0509E
Contextual Info: P R E L IM IN A R Y a Am79C960 PCnet -ISA Singie-Chip Ethernet Controller Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • Single-chip Ethernet controller for the Industry Standard A rchitecture ISA and Extended Industry Standard Architecture (EISA) buses

Contextual Info: ANALOG DEVICES DSP Microcomputer ADSP-2171/ADSP-2172/ADSP-2173 FEATURES 30 ns Instruction Cycle Time 33 MIPS from 16.67 MHz Crystal at 5.0 V 50 ns Instruction Cycle Time (20 MIPS) from 10 MHz Crystal at 3.3 V ADSP-2100 Family Code & Function Compatible with

GG3H

Contextual Info: PRELIMINARY a A m 7 9 C Advanced Micro Devices 9 6 1 A PCnet -ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA DISTINCTIVE CHARACTERISTICS • Single-chip Ethernet controller for the Industry Standard Architecture ISA and Extended

Contextual Info: PRELIMINARY AMD£I Am79C873 NetPHY -1 10/100 Mbps Ethernet Physical Layer Single-Chip Transceiver with 100BASE-FX Support DISTINCTIVE CHARACTERISTICS • 100BASE-FX direct interface to industry standard electrical/optical transceivers ■ High performance 100 Mbps clock generator

MSC 1697 IC pin diagram

Abstract: sf 1565 sg syy 155 415 TC75 Temperature Sensor xo 405 mf DSP5630 timer eft disco TL 434 FM receiver module diagram LG 21 fs 4 bg model circuits
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL Order this document by: DSP56304/D DATA DSP56304 Advance Information 24-BIT DIGITAL SIGNAL PROCESSOR ,*!. ‘*{,3, Motorola designed the ROM-based DSP56304 to support multifunction wireless and eg$\.*:<2~, embedded DSP applications. In addition to the large on-tip ROM spaces, the DSP56304,@~~~}t.”

Contextual Info: AMD£I PRELIMINARY Am79C970A PCnet -PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product DISTINCTIVE CHARACTERISTICS • Single-chip Ethernet controller for the Peripheral Component Interconnect PCI local bus ■ Supports optional Boot PROM for diskless node

Contextual Info: PRELIMINARY AMD£I Am79C873 NetPHY -1 10/100 Mbps Ethernet Physical Layer Single-Chip Transceiver with 100BASE-FX Support DISTINCTIVE CHARACTERISTICS • 100BASE-FX direct interface to industry standard electrical/optical transceivers ■ ■ 10/100BASE-TX physical-layer, single-chip