H987 Search Results

Contextual Info: HMC987LP5E v03.1112 CloCk Distribution - sMt LOW NOISE 1:9 FANOUT BUFFER DC - 8 GHz Typical Applications Features the is suitable for: ultra low noise Floor: -166 dbc/Hz @ 2 GHz • • • • • • • • Wideband: DC - 8 GHz operating Frequency sonEt, Fibre Channel, GigE Clock Distribution

GR-1244-CORE

Abstract: ZL50018 ZL50018GAC ZL50018QCC 99 mfu
Contextual Info: ZL50018 2 K Digital Switch with Enhanced Stratum 3 DPLL Data Sheet Features 2048 channel x 2048 channel non-blocking digital Time Division Multiplex TDM switch at 8.192 and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and/or

ZL50018

Abstract: GR-1244-CORE ZL50018GAC ZL50018QCC MFU 78
Contextual Info: ZL50018 2 K Digital Switch with Enhanced Stratum 3 DPLL Data Sheet Features November 2006 • 2048 channel x 2048 channel non-blocking digital Time Division Multiplex TDM switch at 8.192 and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and/or

Contextual Info: HMC987LP5E v02.0712 Clock Distribution - SMT LOW NOISE 1:9 FANOUT BUFFER DC - 8 GHz Typical Applications Features The is suitable for: Ultra Low Noise Floor: -166 dBc/Hz @ 2 GHz • SONET, Fibre Channel, GigE Clock Distribution • ADC/DAC Clock Distribution

GR-1244-CORE

Abstract: ZL50021 ZL50021GAC ZL50021QCC
Contextual Info: ZL50021 Enhanced 4 K Digital Switch with Stratum 3 DPLL Data Sheet Features 4096-channel x 4096-channel non-blocking digital Time Division Multiplex TDM switch at 8.192 and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and/or

HMC830

Abstract: HMC976LP3E HITTITE CLOCK RECOVERY 10 ghz Material density EN8
Contextual Info: HMC987LP5E v01.0512 Clock Distribution - SMT LOW NOISE 1:9 FANOUT BUFFER DC - 8 GHz Typical Applications Features The is suitable for: Ultra Low Noise Floor: -166 dBc/Hz @ 2 GHz • SONET, Fibre Channel, GigE Clock Distribution • ADC/DAC Clock Distribution

GR-1244-CORE

Abstract: ZL50021 ZL50021GAC ZL50021GAG2 ZL50021QCC
Contextual Info: ZL50021 Enhanced 4 K Digital Switch with Stratum 3 DPLL Data Sheet Features 4096-channel x 4096-channel non-blocking digital Time Division Multiplex TDM switch at 8.192 and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and/or

dpm001

Abstract: N203 zl50018 PMS-100 MFU C0 37 PMS01
Contextual Info: ZL50018 2 K Digital Switch with Enhanced Stratum 3 DPLL Data Sheet Features Ordering Information ZL50018GAC 256 Ball PBGA Trays ZL50018QCC 256 Lead LQFP Trays ZL50018GAG2 256 Ball PBGA* Trays *Pb Free Tin/Silver/Copper 32 serial TDM input, 32 serial TDM output

4MNU

Abstract: R1F100
Contextual Info: ZL50018 2 K Digital Switch with Enhanced Stratum 3 DPLL Data Sheet Features 2048 channel x 2048 channel non-blocking digital Time Division Multiplex TDM switch at 8.192 and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and/or

Philips FA 145

Abstract: FLR13 VCT 492 x GR-1244-CORE ZL50021 ZL50021GAC ZL50021GAG2 ZL50021QCC SCA-7
Contextual Info: ZL50021 Enhanced 4 K Digital Switch with Stratum 3 DPLL Data Sheet Features Ordering Information ZL50021GAC 256 Ball PBGA Trays ZL50021QCC 256 Lead LQFP Trays ZL50021GAG2 256 Ball PBGA* Trays *Pb Free Tin/Silver/Copper 32 serial TDM input, 32 serial TDM output

Contextual Info: P .C .B . H O LE DIM . DRILLED HOLE FIN. HOLE AFTER REFLOW C u -th k s S n P b -th k s AC TIO N PIN :1,15 ± 0 ,0 2 5 :0,94 to 1.09 :0,91 to 1.09 :0,025 to 0 ,0 7 5 :0.004 to 0 .0 1 0 a mm mm mm mm mm DO s NOT D IM EN SIO N S THIRD ANGLE SC ALE IN M E T R I C

Philips FA 145

Contextual Info: ZL50021 Enhanced 4 K Digital Switch with Stratum 3 DPLL Data Sheet Features 4096-channel x 4096-channel non-blocking digital Time Division Multiplex TDM switch at 8.192 and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and/or

Contextual Info: ZL50018 2 K Digital Switch with Enhanced Stratum 3 DPLL Data Sheet Features 2048 channel x 2048 channel non-blocking digital Time Division Multiplex TDM switch at 8.192 and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and/or

top side marking b2

Abstract: Raltron Electronics part marking guide crystal GR-1244-CORE ZL50021 ZL50021GAC ZL50021QCC phase sequence detector cfru TI18
Contextual Info: ZL50021 Enhanced 4 K Digital Switch with Stratum 3 DPLL Data Sheet Features 4096-channel x 4096-channel non-blocking digital Time Division Multiplex TDM switch at 8.192 and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and/or

HMC830

Abstract: HMC830LP6GE Material density EN8 H987 HMC987LP5E HMC830LP6G EKIT01-HMC987LP5E HMC976LP3E C108 J-28
Contextual Info: HMC987LP5E v00.0611 LOW NOISE 1:9 FANOUT BUFFER DC - 8 GHz Typical Applications Features The HMC987LP5E is suitable for: Ultra Low Noise Floor: -166 dBc/Hz @ 2 GHz • SONET, Fibre Channel, GigE Clock Distribution • ADC/DAC Clock Distribution • Low Skew and Jitter Clock or Data Fanout

TI18

Abstract: Raltron Electronics part marking guide crystal
Contextual Info: ZL50018 2 K Digital Switch with Enhanced Stratum 3 DPLL Data Sheet Features 2048 channel x 2048 channel non-blocking digital Time Division Multiplex TDM switch at 8.192 and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and/or

HMC987

Abstract: EKIT01-HMC987LP5E
Contextual Info: HMC987LP5E v03.1112 Clock Distribution - SMT LOW NOISE 1:9 FANOUT BUFFER DC - 8 GHz Typical Applications Features The is suitable for: Ultra Low Noise Floor: -166 dBc/Hz @ 2 GHz • SONET, Fibre Channel, GigE Clock Distribution • ADC/DAC Clock Distribution

Contextual Info: P .C .B . H O LE DRILLED HOLE FIN. HOLE AFTER REFLOW C u— th k s SnPb— thka D IM . A C T IO N :1,15 :Q,94 :0 ,9 1 :0,025 :0,004 PIN ±0,025 to 1.09 to 1.09 to 0,075 to 0,010 TH IR D ANGLE mm mm mm mm mm PROJECTION m ê id # ^ 3 \E M NOTES: /K A / ^ \ CONNECTOR MEETS THE REQUIREMENTS

h945

Abstract: H944 transistor h945 h965 h946 H948 IR1518 BCM56800 h945 transistor H808
Contextual Info: LatticeECP3 and Broadcom 10 Gbps Physical/MAC Layer Interoperability July 2010 Technical Note TN1218 Introduction This technical note describes a Physical/MAC layer 10-Gigabit Ethernet interoperability test between a LatticeECP3 device and the Broadcom BCM56800 network switch. The test exercises the Physical/MAC layer

ZL50018

Abstract: GR-1244-CORE ZL50018GAC ZL50018QCC IEEE 1149.1 JTAG
Contextual Info: ZL50018 2 K Digital Switch with Enhanced Stratum 3 DPLL Data Sheet Features November 2006 • 2048 channel x 2048 channel non-blocking digital Time Division Multiplex TDM switch at 8.192 and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and/or

HMC987

Abstract: HMC830 C106 1112 Material density EN8 EVAL01-HMC987LP5E EKIT01-HMC987LP5E
Contextual Info: HMC987LP5E v03.1112 Clock Distribution - SMT LOW NOISE 1:9 FANOUT BUFFER DC - 8 GHz Typical Applications Features The is suitable for: Ultra Low Noise Floor: -166 dBc/Hz @ 2 GHz • SONET, Fibre Channel, GigE Clock Distribution • ADC/DAC Clock Distribution

h946

Abstract: H945 H944 h965 H924 h940 295050 transistor h945 H948 transistor BC rx
Contextual Info: LatticeECP3 and Marvell 10 Gbps Physical/MAC Layer Interoperability July 2010 Technical Note TN1219 Introduction This technical note describes a Physical/MAC Layer 10-Gigabit Ethernet interoperability test between a LatticeECP3 device and the Marvell Alaska 88X2040 device. The test exercises the Physical/MAC Layer up to

0057H

Abstract: GR-1244-CORE ZL50021 ZL50021GAC ZL50021GAG2 ZL50021QCC
Contextual Info: ZL50021 Enhanced 4 K Digital Switch with Stratum 3 DPLL Data Sheet Features 4096-channel x 4096-channel non-blocking digital Time Division Multiplex TDM switch at 8.192 and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and/or

HMC830

Abstract: Material density EN8 CP1107
Contextual Info: HMC987LP5E HIGH SPEED LOGIC - SMT LOW NOISE 1:9 FANOUT BUFFER DC - 8 GHz Typical Applications Features The is suitable for: Ultra Low Noise Floor: -166 dBc/Hz @ 2 GHz • SONET, Fibre Channel, GigE Clock Distribution • ADC/DAC Clock Distribution • Low Skew and Jitter Clock or Data Fanout