H100I Search Results

Contextual Info: MicroPower Direct Ultra-miniature MiniDIP, 1W High Input/Output Isolation DC/DC Converters H100I Series Key Features Ultra-Miniature MiniDIP Case 1W Output Power 5V, 12V & 24V Inputs 3.0 kVDC Isolation Wide Temperature Operation Low Cost Electrical Specifications

H103I

Abstract: H106I H122 H122I 217F
Contextual Info: H100I Series Ultra-Miniature MiniDIP 1W, High Isolation DC/DC Converters New Models!! Electrical Specifications Specifications typical @ +25°C, nominal input voltage & rated output current, unless otherwise noted. Specifications subject to change without notice.

H123

Abstract: 217F 251C H103I H132I
Contextual Info: MicroPower Direct Ultra-miniature MiniDIP, 1W High Input/Output Isolation DC/DC Converters H100I Series Key Features Ultra-Miniature MiniDIP Case 1W Output Power 5V, 12V, 24V & 48V Inputs 3.0 kVDC Isolation Wide Temperature Operation Low Cost Electrical Specifications

H1000E

Abstract: TNETA1575 TNETA1585 h1001A-1D
Contextual Info: TNETA1585 ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES SDNS041A – NOVEMBER 1996 – REVISED JULY 1998 D D D D D D D D D Single-Chip Scheduler for Scheduling Available Bit Rate ABR Connections Used With the TNETA1575 to Provide a

MT9045

Abstract: MT90503 MT90503AG MT90528 MT9072 MT9076 15 K26 011110 drivers 14K25 894h 0822H1
Contextual Info: MT90503 2048VC AAL1 SAR Data Sheet DS5509 Features • • • • • • AAL1 Segmentation and Reassembly device capable of simultaneously processing up to 2048 bidirectional VCs AAL1 cell format for "Structured DS1/E1 N x 64kbps Service" as per ATM Forum AF-VTOA0078.000 "Circuit Emulation Services

H100I

Abstract: H100F
Contextual Info: MT90503 2048VC AAL1 SAR Data Sheet DS5509 Features • • • • • • AAL1 Segmentation and Reassembly device capable of simultaneously processing up to 2048 bidirectional VCs AAL1 cell format for "Structured DS1/E1 N x 64kbps Service" as per ATM Forum AF-VTOA0078.000 "Circuit Emulation Services

0724H

Contextual Info: MT90503 2048VC AAL1 SAR Data Sheet Features July 2003 • AAL1 Segmentation and Reassembly device capable of simultaneously processing up to 2048 bidirectional VCs • AAL1 cell format for "Structured DS1/E1 N x 64kbps Service" as per ATM Forum AF-VTOA0078.000 "Circuit Emulation Services

H100F

Abstract: H100I
Contextual Info: MT90503 2048VC AAL1 SAR Data Sheet Features July 2003 • AAL1 Segmentation and Reassembly device capable of simultaneously processing up to 2048 bidirectional VCs • AAL1 cell format for "Structured DS1/E1 N x 64kbps Service" as per ATM Forum AF-VTOA0078.000 "Circuit Emulation Services

Contextual Info: Advance information •■ AS29LL800 II 2.2V 1Mx 8/512Kx 16 CMOS Flash EE PROM Features •O rganization: 1M x 8 / 5 1 2 K x 16 • Sector architecture - O ne 16K; tw o 8K; one 32K; and fifteen 64K byte sectors - O ne 8K; tw o 4K; one 16K; and fifteen 32K w o rd sectors

10004H

Abstract: h1001A-1D
Contextual Info: TNETA1585 ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES SDNS041A – NOVEMBER 1996 – REVISED JULY 1998 D D D D D D D D D Single-Chip Scheduler for Scheduling Available Bit Rate ABR Connections Used With the TNETA1575 to Provide a

2SA1341

Abstract: 2SC3395 transistors marking HJ k 2059 TRANSISTOR LCH10 BU 2058 SANYO CP TA RESISTOR 22E 1W transistor npn d 2058
Contextual Info: SANYO SEMI CONDUCTOR 2SA1341, 2SC3395 CORP E2E I> • TTìTOTb 0007325 S ■ T-37-13 T -3 S -U PN P/N P N Epitaxial Planar S ilico n Transisto rs ♦ 2 0 1 8A Switching Applications with Bias Resistances R1=47kO, R2=47kiì 1233C Applications • Switching circuit, inverter circuit, interface circuit, driver circuit.

003C2

Abstract: ST-4094 088AH
Contextual Info: MT90503 2048VC AAL1 SAR Preliminary Information DS5509 ISSUE 1 Features • • • • • • Ordering Information AAL1 Segmentation Reassembly device capable of simultaneously processing up to 2048 bidirectional VCs AAL1 cell format for "Structured DS1/E1 N x

H4003

Abstract: TNETA1575 TNETA1585 h40004 h400141c h10004 h1001A-1D
Contextual Info: TNETA1585 ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES SDNS041 – NOVEMBER 1996 D D D D D D D D Single-Chip Scheduler for Scheduling Available Bit Rate ABR Connections Used With the TNETA1575 to Provide a Complete Solution for Segmentation and

h1001A-1D

Contextual Info: TNETA1585 ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES SDNS041A – NOVEMBER 1996 – REVISED JULY 1998 D D D D D D D D D Single-Chip Scheduler for Scheduling Available Bit Rate ABR Connections Used With the TNETA1575 to Provide a

crl 452

Abstract: DSLAM structure TXC 18 E60 00324H 15 K26 011110 drivers RxBN 726H crl 858 IR 412H vc-4 digital cross connect
Contextual Info: MT90503 2048VC AAL1 SAR Preliminary Information DS5509 ISSUE 1 Features • • • • • • Ordering Information AAL1 Segmentation Reassembly device capable of simultaneously processing up to 2048 bidirectional VCs AAL1 cell format for "Structured DS1/E1 N x

Contextual Info: TNETA1585 ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES SDNS041A – NOVEMBER 1996 – REVISED JULY 1998 D D D D D D D D D Single-Chip Scheduler for Scheduling Available Bit Rate ABR Connections Used With the TNETA1575 to Provide a