H10 795 1 Search Results

Contextual Info: Dual Row Connectors 891-008 and 891-009 Right Angle Mount PCB, Dual Row Nano Connector Thru Hole Type Right Angle Mount PCB Nano Connectors feature gold alloy TwistPin contacts. These nanomimiature connectors offer premium performance and reliability for demanding applications.

Contextual Info: Dual Row Connectors 891-008 and 891-009 Vertical Mount PCB, Dual Row Nano Connector Thru Hole Type Right Angle Mount PCB Nano Connectors feature gold alloy TwistPin contacts. These nanomimiature connectors offer premium performance and reliability for demanding applications.

h10 795 1

Contextual Info: Dual Row Connectors 891-008 and 891-009 Vertical Mount PCB, Dual Row Nano Connector Thru Hole Type Right Angle Mount PCB Nano Connectors feature gold alloy TwistPin contacts. These nanomimiature connectors offer premium performance and reliability for demanding applications.

T9423

Abstract: TQ144 XC9500XL XC95288 XC95288XL W-7510 w7510 k1739
Contextual Info: XC95288XL High Performance CPLD DS055 v1.4 March 19, 2001 5 Features • • • • • • • • • • • 6 ns pin-to-pin logic delays System frequency up to 208 MHz 288 macrocells with 6,400 usable gates Available in small footprint packages - 144-pin TQFP (117 user I/O pins)

PNX8550

Abstract: PNX2015E PNX2015 running message display abstract TDA9975 car subwoofer amplifier schematic circuit diagram schematic diagram hdmi to scart transistor 23AG samsung colour tv kit circuit diagram infineon 128mb pc266
Contextual Info: UM10113 User manual for the PNX2015 family Rev. 01 – 6 May 2005 User manual Document information Info Content Keywords TV810 platform, PNX8550, ATV, ATSC, Jaguar, HD subsystem, AVIP1, AVIP2, Columbus, TV microcontroller. Abstract This user manual provides a functional overview of PNX2015, together with detailed

XC95288XL pinout

Abstract: XC95288XL XC95288XL-7PQ208I XC95288XL-7TQ144I XC95288XL-10PQ208I XC95288XL-10TQ144I marking G18 XC95288XL-10-PQ208 XC95288XL-6FG256C XAPP114
Contextual Info: XC95288XL High Performance CPLD DS055 v1.7 August 21, 2003 5 Features • • • • • • • • • • • 6 ns pin-to-pin logic delays System frequency up to 208 MHz 288 macrocells with 6,400 usable gates Available in small footprint packages - 144-pin TQFP (117 user I/O pins)

TQ144

Abstract: XAPP361 XC9500XV XC95288XV XC95288XV-10 XC95288XV-7
Contextual Info: u XC95288XV High-Performance CPLD R DS050 v2.5 August 21, 2003 5 Features • • • • • • • • 288 macrocells with 6,400 usable gates Available in small footprint packages - 144-pin TQFP (117 user I/O pins) - 208-pin PQFP (168 user I/O pins) - 280-pin CSP (192 user I/O pins)

Contextual Info: XC95288XL High Performance CPLD DS055 v1.6 May 27, 2003 5 Features • • • • • • • • • • • 6 ns pin-to-pin logic delays System frequency up to 208 MHz 288 macrocells with 6,400 usable gates Available in small footprint packages - 144-pin TQFP (117 user I/O pins)

t25 4 k8

Abstract: 513 b14 337 BGA M4-T1 N10 398 w2 i 87 w30 160 AA10 BGA-F17 AF10
Contextual Info: EP20K600E I/O Pins ver. 1.1 I/O & VREF Bank 1 1 – – 1 1 1 – – 8 8 8 8 – – 8 8 8 8 8 – 8 8 8 8 8 – – 8 8 8 8 8 – 8 8 8 8 8 – – 8 8 8 8 8 – 8 Pad Number Orientation 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

AA10

Abstract: AE10 AF10 AG10 AJ10 AK10 EP20K600C AF31
Contextual Info: EP20K600C I/O Pin-Outs ver. 1.0 I/O & VREF Pad Number Bank Orientation Pin/Pad Function 652-Pin BGA 672-Pin FineLine BGA 1,020-Pin FineLine BGA 1 1 – – 1 1 1 – – 8 8 8 8 – – 8 8 8 8 8 – 8 8 8 8 8 – – 8 8 8 8 8 – 8 8 8 8 8 – – 8 8 8

XC95288XL10TQG144I pinout

Abstract: XC95288XL PQG208 XC95288XL pinout XC95288XL-10TQG144C fgg256 XC95288XL XC95288XL-7CS280C XC95288XL-10FGG256I XC95288XL-7TQ144I pqg208
Contextual Info: XC95288XL High Performance CPLD R DS055 v2.1 April 3, 2007 5 Features • • • • • • • • • • • 6 ns pin-to-pin logic delays System frequency up to 208 MHz 288 macrocells with 6,400 usable gates Available in small footprint packages - 144-pin TQFP (117 user I/O pins

XC95288XL-10PQG208I

Abstract: XC95288XL-10TQ144I XC95288XL-10PQG208C XC95288XL XC95288XL-10TQG144C XAPP114 XAPP427 XC9500XL XC95288 xc95288xl-7fg256c
Contextual Info: XC95288XL High Performance CPLD DS055 v1.8 July 15, 2004 5 Features • • • • • • • • • • • 6 ns pin-to-pin logic delays System frequency up to 208 MHz 288 macrocells with 6,400 usable gates Available in small footprint packages - 144-pin TQFP (117 user I/O pins)

Contextual Info: H ig h-Perfor m a n c e s eri es 8 9 Nanominiature Connectors for interconnect applications APRIL 2013 Series 89 nano miniature High density nanominiature Mil qualified and innovative Glenair circular and rectangular solutions N ow available from Glenair: Nanominiature circular and retangular connectors. The

MIP2F3

Abstract: MIP2F4 MIP382 MIP2E7DMY mip2f2 mip291 MIP414S MIP2E5DMY mip411 MIP3E3SMY equivalent
Contextual Info: 2009 ver.2 Semiconductor Selection Guide Microcomputers, Bipolar ICs, Discrete Semiconductors Caution for Safety „ This product contains Gallium Arsenide GaAs . DANGER GaAs powder and vapor are hazardous to human health if inhaled or ingested. Do not burn, destroy, cut, cleave off, or chemically dissolve the

TT 2222 Horizontal Output Transistor

Abstract: FLH 211 ir 222 ccd sharp pv41 20-PIN BE10 LR36685 RJ21P3BA0PT FLH 311
Contextual Info: BACK SHARP R J 2 1 P 3 B A P RJ21P 3 BA0 PT 1/1.8-type Interline Color CCD Area Sensor with 3 300 k Pixels T DESCRIPTION Package : The RJ21P3BA0PT is a 1/1.8-type 9.13 mm solid- 20-pin half-pitch DIP [Plastic] state image sensors that consists of PN photo­

Contextual Info: Revision 5 ex Automotive Family FPGAs Specifications • 3,000 to 12,000 Available System Gates • Maximum 512 Flip-Flops Using CC Macros • 0.22 m CMOS Process Technology • Up to 132 User-Programmable I/O Pins Features • Live on Power-Up • No Power-Up/Down Sequence Required for Supply

TQ144

Abstract: XC9500XV XC95288XV XC95288XV-10 XC95288XV-5 XC95288XV-7 csp192 T9423 w7510
Contextual Info: XC95288XV High-Performance CPLD R DS050 v2.2 August 27, 2001 5 Advance Product Specification Features Power Estimation • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell

2M253

Abstract: EPXA10F1020 af176 AA10 AC10 AD10 AE10 AF10 AG10 E7916
Contextual Info: EPXA10F1020 I/O Pins ver. 1.31 I/O & VREF Bank Pad Number Orientation Pin/Pad Function 1,020-Pin FineLine BGA 13 1 VCCINT VCCINT 13 2 GNDINT GND 13 3 VCCINT VCCINT 13 4 GNDINT GND 13 5 VCCINT VCCINT 13 6 GNDINT GND 13 7 VCCINT VCCINT 13 8 GNDINT GND 9 9 I/O

smd diode J476

Abstract: LP5 ELNA diode sy 170/2 smd J476 RJ3 Elna SYF-1A335M-RJ ELNA RE2 DCK-3R3E224U-E 10 micro farad 25 v electrolytic capacitor 22 35L CAPacitor
Contextual Info: TECHNICAL NOTETECHNICAL NOTE Certifications of of Quality Quality Management ManagementSystem System as (asofofJun. Jun.2007 2006) Certifications (Malaysia) ELNA-LELON ELECTRONICS (SUZHOU)ELECTRONICS CO., LTD. ELNA-LELON (China) (SUZHOU) CO., LTD. (China)

AA10

Abstract: AM11 AN10 AN11 EP20K1500E 709 B34 AE324
Contextual Info: EP20K1500E I/O Pins ver. 1.0 I/O & VREF Bank 1 1 1 – 1 1 1 – – 1 1 1 1 – 8 8 8 8 – – 8 8 8 8 – 8 8 8 8 – – 8 8 8 8 – 8 8 8 8 – – 8 8 8 8 – 8 Pad Number Orientation 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

F33 1067

Abstract: 1010 817 f15 AA10 AM11 AN10 EP20K1500C 837 B34 AM3 940
Contextual Info: EP20K1500C I/O Pin-Outs ver. 1.0 I/O & VREF Bank Pad Number Orientation Pin/Pad Function 652-Pin BGA 1,020-Pin FineLine BGA 1 1 1 – 1 1 1 – – 1 1 1 1 – 8 8 8 8 – – 8 8 8 8 – 8 8 8 8 – – 8 8 8 8 – 8 8 8 8 – – 8 8 8 8 – 1 2 3 4 5 6

XC5402

Abstract: XC5406 XC5410
Contextual Info: f l XILINX XC5400 Hardwire Array Family Preliminary Product Specification Features Description • Mask Programmed version of the XC5200 Field Programmable Gate Array FPGA - Specifically designed for easy XC5200 conversion - Significant cost reduction for high volume

12GSPS

Contextual Info: MAIN FEATURES § § § § § § § § § § § § § § § § § 8-bit resolution. ADC gain adjust. 2 GHz full power input bandwidth. 1 Gsps min sampling rate. SINAD = 45 dB (7.4 Effective Bits) SFDR = 58 dBc @ FS = 1 Gsps, FIN = 20 MHz : SINAD = 44 dB (7.2 Effective Bits) SFDR = 56 dBc

XC5400

Abstract: 63E17 XC5402 XC5410 XC5415 h8 family xc5406 g1189 XC5202 XC5204
Contextual Info: XC5400 HardWire Array Family  Preliminary Product Specification Features Description • Mask Programmed version of the XC5200 Field Programmable Gate Array FPGA – Specifically designed for easy XC5200 conversion – Significant cost reduction for high volume