H.261 DECODER CHIP Search Results

decoder

Abstract: PQFP100 PQFP144 PQFP160 STI3500A mpeg video decoder
Contextual Info: CONSUMER DIGITAL COMPRESSION Type STi3400 STi3430 STi3500A STi3520 STi3520A STi3520M STi4500 STi4510 Description MPEG-1/H.261 Video Decoder MPEG-1 Single-Chip Audio/Video/CD-ROM Decoder MPEG Video Decoder MPEG Audio/MPEG-2 Video Integrated Decoder MPEG Audio/MPEG-2 Video Decoder with Memory Optimization

STI3400

Abstract: SC4361 DD10 DD11 DD12 DD15 CAS IE 116 weighting systems STi-3400 D9883 skip 24 evi 10
Contextual Info: STi3400 MPEG/H.261 VIDEO DECODER . . . . . . . . . . . . REAL-TIME DECODING OF MPEG-1 SIF-525/SIF-625 AND H.261 (CIF/QCIF) VIDEO BITSTREAMS YCBCR OR RGB OUTPUTS COMPATIBLE WITH PAL AND NTSC FORMAT DISPLAYS PROGRAMMABLE PICTURE AND DISPLAY WINDOW FORMAT

FC - 7D 2a2b

Abstract: STI3400 SH340 Variable Length Decoder VLD
Contextual Info: SGS-THOMSON *7M, IlOtglMilLIOT « STÌ3400 MPEG/H.261 VIDEO DECODER • REAL-TIME DECODING OF MPEG-1 SI F-525/SIF-625 AND H.261 (CIF/QCIF) VIDEO BITSTREAMS ■ YC bC r OR RGB OUTPUTS COMPATIBLE WITH PAL AND NTSC FORMAT DISPLAYS ■ PROGRAMMABLE PICTURE AND DISPLAY

BC 1098

Abstract: H.261 decoder chip STI3240 68000 thomson
Contextual Info: ÜtOV 1 9 1992 / = T SGS-THOMSON ^ 7 £ IM » i[L E * Q M ( g S S T Ì3 2 4 0 MPEG/H.261 VIDEO DECODER PRELIMINARY DATA • Real-time decompression of MPEG video and CCITT H.261 bitstream at up to 10 Mbits/sec ■ Supports real tim e decoding of pictures of 352 x

Contextual Info: VP2615 M ITEL _ H.261 Decoder SE M IC O N D U C T O R Supersedes January 1996 edition, DS3479 - 3.0 DS3479 - 4.0 June 1996 FEATURES DESCRIPTION • Inputs run length coded transform data ■ Outputs 8 bit pixels in YUV block format The V P2615 decoder forms part of a chip set for use in

Contextual Info: SK 11 i f r’J3 C ' T* P ï F < J Ç P Y JUNE 1993 3:5 S E M I PRELIMINARY INFORMATION C O N D U C T O R S DS3479 - 1.9 VP2615 H.261 DECODER FEATURES DESCRIPTION H Inputs run length coded transform data • Outputs 8 bit pixels in YUV block format The VP2615 decoder forms part of a chip set for use in

Contextual Info: VP2615 JANUARY 1996 ADVANCE INFORMATION DS3479 - 3.0 VP2615 H.261 DECODER Supersedes version in June 1995 Digital Video & DSP IC Handbook, HB3923-2 FEATURES DESCRIPTION • Inputs run length coded transform data ■ Outputs 8 bit pixels in YUV block format

zr 78 L 03 video images

Contextual Info: LSI LOGIC L64750/51 CCITT Variable Length Coder/Decoder Description The L64750 and L64751 perform the run-length and variable length coding and decoding func­ tions of the CCITT Consultative Committee on International Telephones and Telegraphs , H.261 video compression standard, respectively.

VP510

Contextual Info: VP2615 VP2615 H.261 Decoder Supersedes January 1996 edition, DS3479 - 3.0 DS3479 - 4.0 June 1996 FEATURES DESCRIPTION • Inputs run length coded transform data ■ Outputs 8 bit pixels in YUV block format ■ Up to full CIF resolution and 30 Hz frame rates

Contextual Info: LSI LOGIC L64715 Two-Error Correcting BCH Encoder-Decoder Description The L64715 implements the forw ard error co r­ rection, bit filling and synchronization scheme specified in CCITT Consultative Committee on International Telephones and Telegraphs recom m endation H.261. The forw ard error

fs15 diode

Abstract: fs14 diode 57 fs15 diode fs12 diode H261 VP2611 VP2612 VP2614 VP2615 VP510
Contextual Info: VP2615 VP2615 H.261 Decoder Supersedes January 1996 edition, DS3479 - 3.0 DS3479 - 4.0 June 1996 FEATURES DESCRIPTION • Inputs run length coded transform data ■ Outputs 8 bit pixels in YUV block format ■ Up to full CIF resolution and 30 Hz frame rates

fs15 diode

Abstract: 48 fs15 diode fs14 diode H261 VP2611 VP2612 VP2614 VP2615 VP510 VP520
Contextual Info: VP2615 VP2615 H.261 Decoder Supersedes January 1996 edition, DS3479 - 3.0 DS3479 - 4.0 June 1996 FEATURES DESCRIPTION • Inputs run length coded transform data ■ Outputs 8 bit pixels in YUV block format ■ Up to full CIF resolution and 30 Hz frame rates

Contextual Info: a i GEC PLESSEY SEPTEMBER 1994 ADVANCE INFORMATION SEMICONDUCTORS DS3479 - 2.3 VP2615 H.261 DECODER Supersedes version in December 1993 Digital Video & D S P 1C Handbook. HB3923-1 FEATURES DESCRIPTION Inputs run length coded transform data Outputs 8 bit pixels in YUV block format

fs5 06

Abstract: H261 VP2611 VP2612 VP2614 VP2615 VP510 VP520 VP520S
Contextual Info: VP2615 VP2615 H.261 Decoder Supersedes January 1996 edition, DS3479 - 3.0 DS3479 - 4.0 June 1996 FEATURES DESCRIPTION • Inputs run length coded transform data ■ Outputs 8 bit pixels in YUV block format ■ Up to full CIF resolution and 30 Hz frame rates

VP520

Abstract: VP520S H261 VP2611 VP2612 VP2614 VP2615 VP510 48 fs15 diode fs15 diode
Contextual Info: VP2615 VP2615 H.261 Decoder Supersedes January 1996 edition, DS3479 - 3.0 DS3479 - 4.0 June 1996 FEATURES DESCRIPTION • Inputs run length coded transform data ■ Outputs 8 bit pixels in YUV block format ■ Up to full CIF resolution and 30 Hz frame rates

Contextual Info: LSI LOGIC L64715 Two-Error Correcting BCH Encoder-Decoder Description The L64715 implements the forw ard error co r­ rection, bit filling and synchronization schem e specified in ITU-TSS formerly CCITT recom m endation H.261. The forw ard error correcting code is a 2-error correcting BCH

BCH code

Contextual Info: LSI LOGIC L64715 Two-Error Correcting BCH Encoder-Decoder Description The L64715 implements the forw ard error cor­ rection, bit filling and synchronization schem e specified in IT U -T SS formerly CCITT recom m endation H.261. The forward error correcting code is a 2-error correcting BCH

Contextual Info: 37bflS2B □ □ n b ? b 4 ^ H P L S B Si GEC PL ES S EY S I M I C O N I PRELIMINARY INFORMATION 11 DS3479- 1.9 VP2615 H.261 DECODER FEATURES DESCRIPTION • Inputs run length coded transform data ■ Outputs 8 bit pixels in YUV block format B Up to full CIF resolution and 30 Hz frame rates

Contextual Info: @ VP2615 M IT E L H.261 Decoder S E M IC O N D U C T O R DS3479 - 4.0 June 1996 Supersedes January 1996 edition, DS3479 - 3.0 FEATURES DESCRIPTION • Inputs run length coded transform data ■ Outputs 8 bit pixels In YUV block format ■ Up to full CIF resolution and 30 Hz frame rates

FS15

Abstract: fs15 diode
Contextual Info: S i GEC P I E S S E Y ADVANCE INFORMATION S E M I C O N D U C T O R S DS3479 - 2.3 VP2615 H.261 DECODER Supersedes version in December 1993 Digital Video & D$P 1C Handbook, HB3923-1 DESCRIPTION FEATURES Inputs run length coded transform data Outputs 8 bit pixels in YUV block format

Contextual Info: Si GEC PLESSEY S E M I C O N D U C T O R S D S 3 4 7 9 - 4.0 VP2615 H .261 DECODER Supersedes January 1996 Edition, DS3479-3.0 FEATURES DESCRIPTION Inputs run length coded transform data O u tp u ts 8 bit pixels in YU V block form at U p to fu ll C IF resolution and 30 Hz fram e rates

bdv 83 d

Contextual Info: LSI LOGIC L64750/51 CCITT Variable Length Coder/Decoder D escription The L64750 and L64751 p erfo rm th e ru n -le n g th and v a ria b le le n g th co din g and d e co d in g fu n c ­ tio n s o f th e CCITT C on su lta tive C om m ittee on In te rn a tio n a l Te lep h o ne s and Telegraphs , H.261

H.261 encoder chip

Contextual Info: VPB261 H.261 Evaluation Board Application Note AN146 - 2.1 June 1996 FEATURES EVALUATION BOARD OVERVIEW • Complete evaluation and prototyping system for Mitel Semiconductor H.261 Video Compression/Decompression chipset. RGB format video is input to the board from a source which

ECHO canceller IC

Abstract: h221 HMP8112 HMP8112A HMP8156 HMP8201 HMP8320VCS HMP8364
Contextual Info: HMP8320VCS S E M I C O N D U C T O R ADVANCE INFORMATION Video Conference Solution Chip Set June 1997 Features Description • Fully Compliant with ITU-T H.320 The HMP8320VCS Video Conference Solution chip set is fully compliant with the ITU-T H.320 Teleconferencing standard and designed to run with a host processor. The VCS