GX 110 Search Results

2f 1001

Abstract: 11010 OC-96
Contextual Info: 6. Specifications & Additional Information SIIGX52004-3.0 Transceiver Blocks Table 6–1 shows the transceiver blocks for Stratix II GX and Stratix GX devices and compares their features. Table 6–1. Stratix II GX Features Versus Stratix GX Features Part 1 of 2

10-bit-serdes

Abstract: K280A B010011 8HBC D243
Contextual Info: 2. Stratix II GX Transceiver Architecture Overview SIIGX52002-4.1 Introduction This chapter provides detailed information about the architecture of Stratix II GX devices. Figure 2–1 shows the Stratix II GX block diagram. Figure 2–1. Stratix II GX Transceiver Block Diagram

2f 1001

Abstract: 1100 11010 FD-111 transistor D313 equivalent
Contextual Info: 6. Specifications & Additional Information SIIGX52004-3.1 Transceiver Blocks Table 6–1 shows the transceiver blocks for Stratix II GX and Stratix GX devices and compares their features. Table 6–1. Stratix II GX Features Versus Stratix GX Features Part 1 of 2

EP2SGX60EF

Abstract: CEI 23-16 circuit diagram of PPM transmitter and receiver CPRI multi rate HD-SDI over sdh PRBS10 3G-SDI serializer SIIGX52002-4 k307
Contextual Info: 2. Stratix II GX Transceiver Architecture Overview SIIGX52002-4.2 Introduction This chapter provides detailed information about the architecture of Stratix II GX devices. Figure 2–1 shows the Stratix II GX block diagram. Figure 2–1. Stratix II GX Transceiver Block Diagram

AGX52011-1

Abstract: EPC16 EPCS128 EPCS16 EPCS64
Contextual Info: 11. Configuring Arria GX Devices AGX52011-1.3 Introduction Arria GX II devices use SRAM cells to store configuration data. Because SRAM memory is volatile, configuration data must be downloaded to Arria GX devices each time the device powers up. Arria GX devices can

texas handbook

Abstract: 1008-B
Contextual Info: Section I. Stratix II GX Transceiver User Guide This section provides information on the configuration modes for Stratix II GX devices. It also includes information on testing, Stratix II GX port and parameter information, and pin constraint information.

HD-SDI over sdh

Abstract: GR-253-CORE PRBS31 SMPTE292M SSTL-15 SSTL-18 PRBS-15
Contextual Info: Section I. Arria II GX Device Data Sheet and Addendum This section provides information about the Arria II GX device data sheet and addendum. This section includes the following chapters: • Chapter 1, Arria II GX Device Datasheet ■ Chapter 2, Addendum to the Arria II GX Device Handbook

free verilog code of prbs pattern generator

Abstract: CPRI multi rate digital alarm clock vhdl code 10 band graphic equalizer CEI 23-16 diode handbook HD-SDI over sdh SDH 209 vhdl code for 16 prbs generator vhdl code for phase frequency detector for FPGA
Contextual Info: Section I. Stratix II GX Transceiver User Guide This section provides information on the configuration modes for Stratix II GX devices. It also includes information on testing, Stratix II GX port and parameter information, and pin constraint information.

GX-18H

Abstract: GX-30MB GX-30M
Contextual Info: A m p lifie r b u ilt-in ty p e ^ GX series k Inductive proximity^ r sensors j Wide variation • Ultra small sensor The smallest 03.8mm size GX-3S and GX-3SB in the industry enabling installation anywhere. • Long-distance sensing The non-flush (GX-18H and units suffied by "ML") type is the

Contextual Info: Errata Sheet for Arria II GX Devices ES-01025-3.7 Errata Sheet This errata sheet provides updated information about known device issues affecting Arria II GX devices. Table 1 lists the specific issues and which Arria II GX devices are affected. Table 1. Issues for Arria II GX Devices Part 1 of 2

B17C

Abstract: Chapter 3 Synchronization diode handbook SDI SERIALIZER Semiconductor Reference and Application Handbook AGX52001-2 Voltage-controlled oscillator hd-SDI deserializer LVDS EP1AGX50DF
Contextual Info: Section I. Arria GX Transceiver User Guide This section provides information on the configuration modes for Arria GX devices. It also includes information on testing, Arria GX port and parameter information, and pin constraint information. This section includes the following chapters:

EP2AGX125

Abstract: ALTMEMPHY
Contextual Info: Arria II GX Device Family ES-01025-3.1 Errata Sheet Introduction This errata sheet provides updated information about known device issues affecting Arria II GX devices. Table 1 lists the specific issues and which Arria II GX devices are affected by each

b17c

Abstract: AGX52001-1 AGX52002-1 PMD 1000
Contextual Info: Section I. Arria GX Transceiver User Guide This section provides information on the configuration modes for Arria GX devices. It also includes information on testing, Arria GX port and parameter information, and pin constraint information. This section includes the following chapters:

Contextual Info: Embedded Ultra-Low Power Intel486 GX Processor 1.0 INTRODUCTION This data sheet describes the embedded Ultra-Low Power ULP Intel486™ GX processor. It is intended for embedded battery-operated and hand-held appli­ cations. The embedded ULP Intel486 GX processor

pin configuration of latch switch

Abstract: EP2S15 EP2S180 EP2S30 EP2S60 EP2S90 EPC16 EPCS128 EPCS16 EPCS64
Contextual Info: 13. Configuring Stratix II & Stratix II GX Devices SII52007-4.5 Introduction Stratix II and Stratix II GX devices use SRAM cells to store configuration data. Because SRAM memory is volatile, configuration data must be downloaded to Stratix II and Stratix II GX devices each time the device

ADV1005

Abstract: EP2AGX45DF29C6N rh 115-2 EP2AGX95EF35I5N EP2AGX45DF29I5N EP2AGX65DF29I5N EP2AGX125EF29I3N EP2AGX65 EP2AGX45DF25C6N EP2AGX260FF35C4N
Contextual Info: Revision: 1.0.0 CUSTOMER ADVISORY ADV1005 ADDITIONAL ASSEMBLY SITE FOR THE ARRIA A II GX FBGA PACKAGE Change Description Altera will be introducing Amkor, Korea ATK as an additional assembly source for the Arria® II GX FBGA packagess. The Arria II GX family is currently manufactured out of Amkor,

Contextual Info: Section I. Stratix GX Device Family Data Sheet This section provides the data sheet specifications for Stratix GX devices. It contains feature definitions of the internal architecture, configuration information, testing information, DC operating conditions,

MV-GX Series

Abstract: 16MV470 Sanyo ax gx Aluminum Electrolytic Capacitors sanyo ag sanyo mv-gx mv-gx capacitors capacitors Ax SANYO ELECTROLYTIC AX SANYO CAPACITORS SERIES AG Sanyo Electrolytic Capacitors sanyo ag
Contextual Info: Miniature Aluminum Electrolytic Capacitors MV-GX/AX Low impedance, Long life solvent proof Series MV-GX/AX series is low impedance and long life. It is suitable for switching power supply, noise limiter etc. Solvent proof (within 5 minutes). • Specifications

pin configuration of buffer

Abstract: EP2AGX125 EP2AGX190 EP2AGX260 EP2AGX45 EP2AGX65 EPCS128 EPCS16 EPCS64 JESD-71
Contextual Info: 9. Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices AIIGX51009-3.0 This chapter contains information about the Arria II GX supported configuration schemes, instructions about how to execute the required configuration schemes, and

hd-SDI deserializer LVDS

Abstract: PMD 1000 digital clock notes SDI SERIALIZER AGX52002-2 pmd1000
Contextual Info: 2. Arria GX Transceiver Protocol Support and Additional Features AGX52002-2.0 Introduction Arria GX transceivers have a dedicated physical coding sublayer PCS and physical media attachment (PMA) circuitry to support PCI Express (PIPE), Gigabit Ethernet (GIGE), and Serial RapidIO protocols.

diagram remote control receiver and transmitter

Abstract: remote protocol universal remote AGX52012-1 EPC16 EPCS128 EPCS16 EPCS64 remote system upgrades
Contextual Info: 12. Remote System Upgrades with Arria GX Devices AGX52012-1.2 Introduction System designers today face difficult challenges such as shortened design cycles, evolving standards, and system deployments in remote locations. Arria GX FPGAs help overcome these challenges with their inherent

k241

Abstract: 1000BASE-X h17c 8HBC
Contextual Info: 6. GIGE Mode SGX52006-1.2 Introduction The Gigabit Ethernet GIGE mode in Stratix GX devices supports a subset of the IEEE GIGE standard. Stratix GX devices have Physical Coding Sub-layer (PCS) functions and Physical Medium Attachment (PMA) functions as Hard Intellectual Property (IP).

tx2/rx2

Abstract: OC48 verilog code for fibre channel
Contextual Info: 3. Stratix II GX Dynamic Reconfiguration SIIGX52007-1.1 Introduction The Stratix II GX gigabit transceiver block gives you a simplified means to dynamically reconfigure: • ■ ■ ■ ■ Transmit and receive analog settings Transmit data rate in the multiples of 1, 2, and 4

CY7C1313V18

Abstract: EP1S60 RLDRAM
Contextual Info: 3. External Memory Interfaces in Stratix & Stratix GX Devices S52008-3.3 Introduction Stratix and Stratix GX devices support a broad range of external memory interfaces such as double data rate DDR SDRAM, RLDRAM II, quad data rate (QDR) SRAM, QDRII SRAM, zero bus turnaround (ZBT)