GG14 Search Results

Contextual Info: b lE D • bSM 'lñB'i M IT S U B IS H I GG14540 122 DISC R ETE SC ■ N ITS MITSUBISHI LASER DIODES ML4XX3 SERIES FOR OPTICAL INFORMATION SYSTEMS ML4403, ML4403R, ML4413N, NAME ML4413C type DESCRIPTION FEATURES ML4XX3 is an AIGaAs semiconductor laser Which

Contextual Info: SAM S UN G E L E C T R O N I C S INC b4E » • 7^4142 KMM581020AN GG14454 455 ■ SM6K DRAM MODULES 1 M x 8 DRAM SIMM Memory Module with Low Power GENERAL DESCRIPTION FEATURES • Performance range: KMM581020AN-7 • • • » • • • tiuc tcAc I rc

seven transistor drivers

Abstract: 251C M54524P WI54524P LF400
Contextual Info: b3E b24TflP7 GG14TflM 213 !•■ M I T B M ITSUBISHI BIPOLAR DIGITAL ICs M54524P MITSUBISHI DGTL LOGIC 7-UNIT 500mA DARLINGTON TRANSISTOR ARRAY W ITH CLAMP DIODE DESCRIPTION PIN CONFIGURATION (TOP VIEW) The M54524P, 7-channel sink driver, consists of 14 NPN tran­

IRF1010S

Abstract: AIT smd
Contextual Info: MÖ55HS2 GG14Ö00 International k Rectifier =163 • IN R PD-9.923 IRF1010S INTERNATIONAL HEXFET® Power M O SFET RECTIFIER Advanced Process Technology Ultra Low On-Resistance Surface Mount Available in Tape & Reel Dynamic dv/dt Rating Repetitive Avalanche Rated

C67078-A1101-A2

Contextual Info: öö» D • ÔSBSbOS GG14ö7b b ■ SIEG 88D 14876 D 7 BUZ 201 SIEMENS AKTIENGESELLSCHAF-Main ratings N-Channel Draln-source voltage l^ S Continuous drain current h Draln-source on-reslstance R,OS on) Description Case = 400 V « 12,5 A = 0,4 n FREDET with fast-recovery reverse diode, N-channel, enhancement mode

Contextual Info: SAMSUNG ELECTRONICS INC b4E ]> • GG1472D AIS «SI1GK 7WIHE KMM532512W/WG DRAM MODULES 512K.X32 DRAM SIMM Memory Module FEATURES GENERAL DESCRIPTION • P e rfo rm a n c e range: The Samsung KMM532512W is a 512K bit x 3 2 Dynam­ ic RAM high density memory module. The Samsung

Contextual Info: öö» D • ÔSBSbOS 88D GG14ö7b 14876 D b « S IE G ~T~ 3 BUZ 201 SIEMENS AKTIENGESELLSCHAF-Main ratings N-Channel Draln-source voltage Continuous drain current Draln-source on-reslstance Description C ase yD3 = 400 V /D = 12,5 A R„S(on = 0,4 i i

BUZ41A

Contextual Info: SILICONIX INC 1ÖE » • Ô2S473S O G m b Q T Ö BUZ41A fsr Siliconix in c o r p o r a t e d N-Channel Enhancement Mode Transistor TO-220AB TOP VIEW ~Ô~ PRODUCT SUMMARY V BR|DSS 'W 500 1.5 •d (A 4.5 1 GATE 2 DRAIN (Connected to TAB) 3 SOURCE ABSOLUTE MAXIMUM RATINGS (Tc = 25°C Unless Otherwise Noted)

Contextual Info: SILICONIX INC lflE D • A5 S4 7 3 5 D014bl3S Q ■ BUZ32 N-Channel Enhancement Mode Transistor TO-220AB TOP VIEW O PRODUCT SUMMARY Id . A V(BRJDSS 200 0.40 9.5 i 1 GATE 2 DRAIN (Connected to TAB) 3 SO U R C E 23 ABSOLUTE MAXIMUM RATINGS (Tc = 25°C Unless Otherwise Noted)

A63A

Abstract: 74LSOO
Contextual Info: •Quadruple 2-input Positive AND Gates with Open Collector Outputs IP IN ARRANGEMENT ¡C IR C U IT S C H E M A T IC ^ ) •RECOM M ENDED OPERATING CONDITIONS Symbol min typ max High level output voltage Item VOH - - 5.5 Unit V Low level output current IOL

DIVIDE-BY-256

Abstract: ONU block diagram 74LSOO HD74LS393 a63a
Contextual Info: •D u a l 4-bit Binary Counters This circuit contains eight master-slave flip-flops and ad­ ditional gating to implement tw o individual four-bit counters. The HD74LS393 comprises tw o independent four-bit binary counters each having a clear and a clock input.

74LSOO

Abstract: HD74LS490
Contextual Info: HD74LS490. This c irc u it d itio n a l contains gating to eigh t master-slave im p le m e n t tw o Dual 4 -b it Decade Counters flip -flo p s ind ividu al 4 -b it and ad ­ I BLOCK DIAGRAM K decade counters. Each decade c o u n te r has ind ividu al clo ck, clear, and

74LSOO

Abstract: HD74LS642 Hitachi Scans-001
Contextual Info: ♦ O c ta l Bus Transceivers inverted open-collector outputs This octal bus transceiver is designed fo r asynchronous two-way communication between data buses. The devices transmit data from the A bus to the B bus or from the B bus to the A bus de­ pending upon the level at the direction control (D IR ) input. The

74LSOO

Contextual Info: •Quadruple 2-input Positive NAND Gates with Open Collector Outputs •C IR C U IT S C H E M A T IC ^ ) BPIN ARRANGEMENT ■RECOMMENDED OPERATING CONDITIONS Symbol min typ max High level output voltage y oh - - 5 .5 Low level output c u rre n t IO L - -

74LSOO

Abstract: 1S2074
Contextual Info: •Q u a d ru p le 2-input Positive N AND Schmitt-triggers •C IR C U IT S C H EM A TIC ^ HPIN ARRANGEMENT ■ELECTRICAL CHARACTERISTICS ( Ta= - 20- + 75”C ) Item Symbol min typ* max Unit Vt + V cc — 5V T e s t Conditions 1.4 1.6 1.9 V Vt ~ V cc — 5V

74LSOO

Abstract: HD74LS367A kl66
Contextual Info: HD74LS367A * Hex Bus Drivers non-inverted data outputs with three-state outputs I PIN ARRANGEMENT I CIRCUIT SCHEMATIC D r i v e r se c tio n (1 / 6 ) C o n t r o l se c tio n Ootpu Control Ci ~ï7 ]vVcc — 1Output Cont roi Ci 'vLLKy L jc t-E I 6 " Y r]D *

ATML U 010

Abstract: ATML H 010 1S2074 400M 74LSOO HD74LS139 OG-16 L400M ATML 010
Contextual Info: H D 74LS139. Dual 2-line-to-4-line Decoders/Demultiplexers IPIN ARRANGEMENT The H D74LS139 comprises two individual two-line-to-fourline decoder in a single package. The active-low enable input can be used as a data line in demultiplexing applications. IBLOCK DIAGRAM

HD74LSoop

Abstract: 1S2074 74LSOO HD74LS195A Hitachi Scans-001 Scans-0014928
Contextual Info: H D 74 L S 19 5A . 4-b¡t Parallel-Access Shift Registers This 4-bit register features parallel inputs, parallel outputs. is loaded into the associated flip-flop and appears at the out­ puts after the positive transition of the clock input. During loading, serial data flow is inhibited. Shifting is accomplished

Contextual Info: •Quadruple 2-input High-voltage Interface Positive NAND Gates • C IR C U IT SC H EM A TIC O ^ B P IN ARRANGEMENT ■RECOM M ENDED OPERATING CONDITIONS Item S ym bol High lev e l o u tp u t v o lta g e Voh L ow lev el o u tp u t c u r r e n t min ty p

Contextual Info: •D u a l 4-input Positive AND Gates •PIN ARRANGEMENT ICIRCUIT SCHEMATICO^ ■ELECTRICAL CHARACTERISTICS Item Input voltage O utput voltage Symbol VlH VlL VOH V>L I ih It L ¡1 Input c u rren t S h o rt-c irc u it output c u rren t Supply c u rren t Input clam p voltage

Contextual Info: Integrated Device Technology, Inc* Single, double-frequency clock input 16.67MHz, 20MHz, 25M Hz and 33MHz operation 16MIPS a t2 0M H z Low cost 84-pin PLCC packaging O n-chip 4-deep write buffer elim inates memory write stalls O n-chip 4-word read buffer supports burst o r sim ple block

Contextual Info: HE8813VG GaAIAs IRED Description The HE8813VG is a 880 nm band GaAIAs infrared light emitting diode with a double heterojunction struc­ ture. It is suitable as a light source for still camera autofocus mechanisms. Features Package Type HE8813VG: VG • High efficiency and high power output

74LSOO

Abstract: HD74LS374 HD74LSoop
Contextual Info: HD74LS374 • O c t a l D-type Edge-triggered Flip-Flops with th ree-state IP IN ARRANGEM ENT The H D74LS374, 8-bit registers features totem-pole threestate outputs designed specifically for driving highly-capacitive or relatively iow-impedance loads. The high-impedance third

1S2074

Abstract: 74LSOO HD74LS75 Hitachi Scans-001
Contextual Info: •Q uad ru ple Bistable Latches The H D 74LS75 is ideally suited for use as temporary storage for binary information between processing units and input/ • P IN ARRANGEMENT output or indicator units. Information present at a data D input is transferred to the Q output when the enable (G) is