GENRAD Search Results

GR2286

Abstract: GR2284i 100N XC2064 XC3090 XC4005 XC5210 XC9500 SVF Series GR2281i
Contextual Info: Programming Xilinx XC9500 CPLDs on GENRAD Testers Preface JTAG Programmer Version Creating GenRad Test Files Table of Contents Introduction Creating SVF Files Revision 1.3 November 20, 1998 Printed in U.S.A. svf2dts Conversion Utility R The Xilinx logo shown above is a registered trademark of Xilinx, Inc.

GR228X

Contextual Info: ON-BOARD PROGRAMMING EQUIPMENT GENRAD GR228X i Series Production Test Systems • ■ ■ ■ ■ On-board programming of Intel Flash memory devices Change data sets on the fly Automatic program file conversion Highest throughput test programming available

561k

Abstract: RL-7533
Contextual Info: Radial Leaded R.F. 0.30 Max. 0.20 0.31 Max. ø0.05 0.20 Notes: 1 Inductance Range: 10µh to 82µh measured on HP4342A Q-meter at 2.5Mhz. (2) Inductance Range: 100µH - 1.000 µH measur ed on GenRad 1658 Dig iBridge. (3) Rated DC tested at 1kHz, I, dc is the minim um current at which the

RL95-582K

Contextual Info: RL95 Radial Leaded R.F. 0.43 Max. 0.20 0.34 Max. MARKING Inductance value 0.32 0.20 PACKAGING Bulk or tape and reel Notes: 1 Inductance Range: 10µh to 82µh measur ed on HP4342A Q-meter a t 2.5Mhz. INDUCTANCES 10µH to 47,000µH (2) Inductance Range: 100µH - 1.000µH measur ed on GenRad 1658 Dig iBridge.

Genrad 228X

Abstract: xc9572xl pin configuration xilinx xc95108 jtag cable Schematic XC9572XL Series GR228X Xilinx jtag cable pcb Schematic 15N35 dts circuit board 22N55 n43 414
Contextual Info: Programming Xilinx XC9500/XL/XV CPLDs on GENRAD Testers Preface Introduction Creating SVF Files Creating GenRad Test Files DTS Example and Explanation Revision 1.5 Optimizations December 1, 1999 Printed in U.S.A. svf2dts Conversion Utility R The Xilinx logo shown above is a registered trademark of Xilinx, Inc.

Contextual Info: Press Release CYPRESS ANNOUNCES ATE SUPPORT FOR ULTRA37000 CPLDS Combination of Device Programming and Board Testing Streamlines Manufacturing Flow SAN JOSE, California…August 19, 1999 - Cypress Semiconductor Corporation NYSE:CY today announced that it has complete programming support available on Genrad, Hewlett-Packard, and

IET Labs

Abstract: 143339
Contextual Info: Contents p. 2 Applic. pp. 4-8 GenRad products pp. 50-87 Products pp. 12-87 Selection pp. 9-11 Precision Decade Resistor Index p. 89 Accurate, Stable and Low Zero Resistance GenRad 1433 Series p. 1 of 2 The 1433 Decade Resistors are primarily intended for precision measurement applications where

XC-DS501

Abstract: XC2064 XC3090 XC4005 XC5210 XC9500 dts 603 GR2281i ABEL-HDL Reference Manual
Contextual Info: Programming Xilinx XC9500 CPLDs on GENRAD Testers Preface EZTag Version Creating Compiled Test Files April 14, 1997 Version 1.0 Table of Contents Introduction Creating SVF Files Printed in U.S.A. svf2dts Conversion Utility R The Xilinx logo shown above is a registered trademark of Xilinx, Inc.

RL544

Abstract: 561k RL-54
Contextual Info: RL54 Radial Leaded R.F . 0.20 Max. 0.20 ±/-1.0 0.157 0.24 0.028 MARKING Inductance value Notes: 1 Inductance Range measur ed on HP4342A Q-meter. PACKAGING Bulk or Tape and Reel (2) Inductance Range: 100µH - 1.000 µH measur ed on GenRad 1658 DigiBr idge.

1433-39A

Contextual Info: GenRad 1433 Series Precision Decade Resistor p. 1 of 2 The 1433 Decade Resistors are convenient resistance standards for checking the accuracy of resistance-measuring devices. They are primarily intended for precision-measurement applications where accuracy, stability, and low-zero-resistance

GR2284i

Abstract: GenRad teradyne teradyne tester test system XC2064 XC3090 XC4005 XC5210 XC9500 dts 603
Contextual Info: Programming Xilinx XC9500 CPLDs on GENRAD Testers Preface EZTag Version Creating GenRad Test Files Table of Contents Introduction Creating SVF Files Revision 1.1 March 30, 1998 Printed in U.S.A. svf2dts Conversion Utility R The Xilinx logo shown above is a registered trademark of Xilinx, Inc.

gr228x

Abstract: 28F001BX 28F002BC 28F002BX 28F010 28F020
Contextual Info: ON-BOARD PROGRAMMING EQUIPMENT GENRAD GR228X i Series Production Test Systems • ■ ■ ■ ■ On-board programming of Intel Flash memory devices Change data sets on the fly Automatic program file conversion Highest throughput test programming available

Contextual Info: RL64 Radial Leaded R.F . 0.26 Max. 0.20 0.158 0.24 0.028 MARKING Inductance value Notes: 1 Inductance Range measur ed on HP4342A Q-meter. PACKAGING Bulk or Tape and Reel. (2) Inductance Range: 100µH - 1.000µH measured on GenRad 1658 Dig iBr idge. INDUCTANCES 22µH to 1,000µH

TB-2082

Abstract: TB208 470-2075-100 reballing programming smt machine 470-1075-100 470-3105-100 programming for smt machine C-471-1025-500 Amphenol MIL CIRCULAR CONNECTORS
Contextual Info: AMPHENOL TCS TB-2082 DFM and SMT Assembly Guideline Revision “F“ Specification Revision Status Revision SCR No. Description Initial Date “-“ “A” 33277 36994 J. Marvin J. Proulx 1/16/01 10/19/01 “B” “C” 39831 42921 J. Proulx J. Proulx 9/17/02

2032LV

Abstract: teradyne z1800 tester manual teradyne z8000 tester manual 1016E 1032E 1048C 3256E pDS4102-J44 Quasar gr228x
Contextual Info: ISP Daisy Chain Download Reference Manual Version 5.0 Technical Support Line: 1-800-LATTICE or 408 428-6414 pDS4104 -RM Rev 5.0 Copyright This document may not, in whole or part, be copied, photocopied, reproduced, translated, or reduced to any electronic medium or machine-readable form without

conversion software jedec lattice

Abstract: isp Cable lattice sun LATTICE 3000 SERIES lattice 22v10 programming
Contextual Info: TM ISP Daisy Chain Download Software provides an efficient method for programming Lattice ISP and ispJTAG devices from the logic design JEDEC file generated by any Lattice Compiler tool. ISP Daisy Chain Download software allows you to quickly and easily program devices using specific commands like Program

teradyne tester test system

Abstract: Z1800 teradyne XC9500
Contextual Info: Integrating XC9500 ISP Capabilities With Manufacturing Test on the Teradyne Z1800 I n-system programming ISP allows you to program and re-program devices that are already soldered on a system board. ISP streamlines manufacturing flows, allows you to update and reconfigure remote systems,

XAPP393

Abstract: DS090 VQ100 XC2C128 XC2C256 XC2C32 XC2C384 XC2C64 interfacing 8051 XC9500 cpld pins table
Contextual Info: R CoolRunner-II CPLD Family DS090 v1.7 October 2, 2003 Preliminary Product Specification Features • • • • Optimized for 1.8V systems - Industry’s fastest low power CPLD - Static Icc of less than 100 microamps at all times - Densities from 32 to 512 macrocells

COOLRUNNER-II examples

Abstract: XA CoolRunner-II XAPP393 VQG44 CoolRunner-II CPLD AEC-Q100 TS16949 XA2C128 XA2C256 XA2C32A
Contextual Info: CoolRunner-II CPLD XA Product Family R DS315-1 v1.0 October 18, 2004 Advance Product Specification Features • • • • • AEC-Q100 device qualification and full PPAP support available in both extended temperature Q-grade and I-grade. Optimized for 1.8V systems

transistor AE code PNP smd

Abstract: OPA71 cmos opamp OPA41 5 STKM2000 smd transistor code SG
Contextual Info: STKM2000 SERIES 2 µ/2 POLY/2 METAL BiCMOS MIXED ANALOG-DIGITAL STANDARD CELLS • ■ ■ ■ ■ ■ ■ ■ ADVANCED BICMOS 2 µ/2 POLY/ 2 METAL PROCESS TWIN TUB PROCESS HIGH LATCH-UP IMMUNITY POWER SUPPLY : MAXIMUM RATING : -0.5V TO 12V OPERATING CONDITIONS : 3V TO 10V

Behavioral verilog model

Abstract: "li shin" ac adapter
Contextual Info: MACH 5A Family BEYOND PERFORMANCE Fifth G eneration MACH A rchitecture UNIQUE FEATURES ♦ High Densities and l/Os — 6 Macrocell options 128 to 512 — 6 I/O options (74 to 256) — 1 6 - 6 4 o u tp u t enables — Up to 5 I/O options per macrocell — Up to 6 density & I/O options fo r each package

Contextual Info: PRELIMINARY VANTIS BEYO N D PERFO RM A N C E COM'L: -7/10/12/15 IND: -10/12/14/18 MACH 4-192/MACH4LV-192 High-Performance EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ 144 pins in TQFP

DC MOTOR SPEED CONTROL USING VHDL xilinx

Abstract: xilinx vhdl rs232 code gr228x structural vhdl code for ripple counter xilinx uart verilog code xilinx xc9536 digital clock PCIM 164 PCIM 176 XC4013XL PIN BG256 MATROX Mil
Contextual Info: XCELL Issue 27 First Quarter 1998 THE QUARTERLY JOURNAL FOR XILINX PROGRAMMABLE LOGIC USERS PRODUCT INFORMATION FOUR New FPGA Families! The Programmable Logic CompanySM Inside This Issue: GENERAL Record-Breaking Technology Today . 2 1998 Data Book . 3

Contextual Info: FINAL COM’L: Q-10 c\ Advanced Micro Devices PALCE22V10Q-10 24-Pin EE CMOS Versatile PAL Device DISTINCTIVE CHARACTERISTICS • 10 ns propagation delay ■ 83 MHz fMAX external ■ Low-power EE CMOS ■ 10 macrocells programmable as registered or combinatorial, and active high or active low to